The DRAM controller directly controls the DRAM (dynamic random access memory). The DRAM control pins are lo-cated at ports P104/CAS, P105/RAS, P106/MAs, P107/MAg, and Ao/MAo through A7/MA7.
Figure 73 shows the DRAM controller block diagram. Fi-gure 74 shows the DRAM control register (address 6416 )
bit configuration. Bit 7 of the DRAM control register is a DRAM validity bit. When this bit is set to "1", port P104
serves as the CAS (column address strobe) signal output pin, port 105 serves as the RAS (Row address strobe) sig-nal output pin, port P106 serves as the MAs output pin, and P107 serves as the MAg output terminal. Upon resetting, the DRAM validity bit is set to "0". When using the DRAM con-troller, be sure to set this bit to "1".
Bits 0 through 3 of the DRAM control register are the DRAM area selection bits. These bits are used to desig-nate the DRAM area in 1 M-byte units. When the DRAM area selection bits (bits 3 through 0) are set to "0000", the DRAM controller concludes that there is no DRAM area.
This state prevails upon resetting. When the bits are set to
"0001", the DRAM area is set to 1M-byte and the system automatically judges that the area between addresses F0000016 and FFFFFF16 is provided as the DRAM area.
When the bits are set to "1111", the DRAM area is set to 15M bytes and the DRAM controller automatically con-cludes that the area between addresses 10000016 and FFFFFF16 is the DRAM area.
When the area to be accessed is judged to the DRAM area, the DRAM controller generates timing signals RAS
Refresh request
1116
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DRAM area selection bit 0000 : No DRAM area 0001 : FOOOOO- FFFFFF 0010 : EOOOOO- FFFFFF 0011 : DOOOOO-FFFFFF1100: 400000-FFFFFF 1101 : 300000-FFFFFF 1110 : 200000- FFFFFF 1111 : 100000- FFFFFF ' - - - DRAM validity bit
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Invalid 1 : Valid Fig.74 DRAM control register bit configurationand CAS for latching the address in the bus cycle, and out-puts addresses Ao through A20 to MAo (Ao pin) through MA7 (A7 pin), MA8 , and MAg by means of time division multi-plexing: The time division multiplexing method varies with the external bus connection. Table 7 shows the address time-division multiplexing DRAM controller for DRAM accessing.
It should also be noted that when the DRAM area is acces-sed, the "L" level period of E is increased twofold without respect to the contents of the wait bit. This also holds true when the DRAM area is accessed by the CPU or DMA controller.
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Fig.73 DRAM controller block diagram
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The DRAM controller incorporates an independent 8-bit re-fresh timer. The rere-fresh timer is based on decrement count and its clock source employs a clock that is derived by di-viding f(X,N) by sixteen. The refresh interval can be given as desired by writing a value (not "0") in the refresh timer (address 6616 ), The value must be set in the refresh timer before the DRAM validity bit is set to "1". Generally, the value written in the refresh timer is expressed by the fol-lowing formula.
Timer value n=refresh interval [ns] X f(X'N)/16-1 When the contents of the refresh timer is 00,6, the refresh timer generates the refresh request signal. The refresh re-quest signal sends the bus use rere-quest to the bus access controller. When the request is accepted, the system stops the CPU and DMA controller and sends the response sig-nal to the RAS/CAS generator circuit. The RAS/CAS gener-ator circuit generates the refresh cycle.
If the CPU or DMA controller is using the data bus, refresh cycle generation does not take place even when the re-fresh request is made. When a WIT or STP instruction is executed, the refresh operation is not performed. Figure 75 shows an example refresh operation that is performed when the refresh request is made during DMA transfer. Fi-gure 76 shows an example refresh operation that is per-formed when the refresh request is made during CPU op-eration (bus accessing). Both examples represent the
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cases where the response delay time is maximized. Table 8 shows the delay time that denotes the interval between the instant at which the contents of the refresh timer be-come 00'6 and the instant at which the refresh cycle is in-serted. This table indicates the maximum and m.inimum values prevailing when the RDY input is not provided. If the access time is to be increased by RDY input, the time de-lay resulting from such an access time increase must be added to the maximum values in the table.
Figure 77 shows the DRAM accessing bus cycle timing dia- . gram. The DRAM controller generates three types of bus cycles: read, write, and refresh bus cycles.
In the read cycle, the RAS pin level falls from "H" to "L", and then the CAS pin level falls from "H" to "L" at the end of 1 12 the internal clock cycle ¢. The address bus changes from the row address to the column address during the time interval between RAS pin level fall and CAS pin level fall.
In the write cycle, the CAS pin level falls one internal clock cycle ¢ after RAS pin level fall.
In the refresh cycle, the CAS pin level falls 112 internal clock cycle ¢ earlier than RAS pin level fall. Refresh occurs as the CAS pin level falls earlier than the RAS pin level.
This method is called the "CAS before RAS refresh method". Be sure that the selected DRAM permits "CAS before RAS refresh".
Table 7. DRAM accessing address time-division multiplexing method
~
Regular bus AD A, A, A3 A4 A5 Ao A7 P10. P107DRAM access MAo MA, MA, MA3 MA4 MA5 MA. MA7 MAs MAg
External 8-bit Row address AD A, A, A3 A4 A5 As A7 A16 A,S
Column address As A9 A10 An A" A13 A14 A'5 A17 A'9
External 16-bit Row address A16 A, A, A3 A4 A5 As A7 A,s A'D
Column address As Ag A10 A" A12 A13 A'4 A'5 A17 A'9
Table 8. Refresh wait time Cause of bus use Number of delay
cycles At 16MHz At 8MHz
CPU 1.5"",6.5 187.5ns-812.5ns (wait provided) 375ns-1625ns (wait provided)
187.5ns-562.5ns (wait not provided) 375ns-1125ns (wait not provided)
DMA controller 1.5-12.5 187.5ns-1562.5ns (wait provided) 375ns-3125ns (wait provided)
187.5ns-1062.5ns (wait not provided) 375ns-2125ns (wait not provided)
HOLD state 1.5 187.5ns 375ns
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Row address (2) Timing diagram at writingMITSUBISHI MICROCOMPUTERS
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