Memory-Management Registers

Four registers of the Intel486 processor specify the location of the data structures which control segmented memory management, as shown in Figure 4-2. Special instructions are provided for loading and storing these registers. The GDTR and IDTR registers may be loaded with instructions which get a six-byte block of data from memory. The LDTR and TR registers may be loaded with instructions which take a 16-bit segment selector as an operand. The remaining bytes of these registers are then loaded automatically by the processor from the descriptor referenced by the operand.

Most systems will protect the instructions which load memory-management registers from use by application programs (although a system in which no protection is used is

possible). . .

GDTR Global Descriptor Table Register

This register holds the 32-bit base address and .16-bit segment limit for the global descriptor table (GDT). When a reference is made to data in memory, a segment selec-tor is used to find a segment descripselec-tor in the GDT or LDT. A segment descripselec-tor contains the base address for a segment. See . Chapter ·5 for an explanation of segmentation.

LDTR Local Descriptor Table Register

This register holds the 32-bit base address, 16-bit segment limit, and 16-bit segment selector for the local descriptor table (LDT). The segment which contains the LDT has a segment descriptor in the GDT. There is no segment selector for the GDT. When a reference is made to data in memory, a segment selector is used to find a segment descriptor in the GDT or LDT. A segment descriptor contains the base address fora segment. See Chapter 5 for an explanation of segmentation. .

SYSTEM ADDRESS REGISTERS

47 32-BIT UNEAR BASE ADDRESS 16 15 LIMIT o

SYSTEM SEGMENT REGISTERS

15 o

TR SELECTOR LDTR SELECTOR

DESCRIPTOR REGISTERS (AUTOMAnCALLY LOADED) 32-BIT LINEAR BASE ADDRESS 32-BIT SEGMENT UMIT ATTRIBUTES

II ^II

240486;4-2

Figure 4·2. Memory Management Registers

SYSTEM ARCHITECTURE

IDTR Interrupt Descriptor Table Register

This register holds the 32-bit base address and 16-bit segment limit for the interrupt descriptor table (IDT). When an interrupt occurs, the interrupt vector is used as an index to get a gate descriptor from this table. The gate descriptor contains a pointer used to start up the interrupt handler. See Chapter 9 for details of the interrupt mechanism.

TR Task Register

This register holds the 32-bit base address, 16-bit segment limit, descriptor attributes, and 16-bit segment selector for the task currently being executed. It references a task state segment (TSS) descriptor in the global descriptor table. See Chapter 7 for a description of the multitasking features of the Intel486 processor.

4.1.3 Control Registers

Figure 4-3 shows the format of the control registers CRO, CR1, CR2, and CR3. Most systems prevent application programs from loading the control registers (although an unprotected system would allow this). Application programs can read this register to determine if a numerics coprocessor is present. Forms of the MOV instruction allow the register to be loaded from or stored in general registers. For example:

MDV EAX, CR9 MDV CR3, EBX

The CRO register contains system control flags, which control modes or indicate states which apply generally to the processor, rather than to the execution of an individual task.

A program should not attempt to change any of the reserved bit positions. Reserved bits should always be set to the value previously read.

3

1 2

3 ¹ 5

PAGE DIRECTORY BASE REGISTER (PDBR)

PAGE FAULT LINEAR ADDRESS

RESERVED

RESERVED

Figure 4-3. Control Registers

D CR3

CR2

CR1

CRD

240486i4·3

SYSTEM ARCHITECTURE

The LMSW instruction can only modify the lower 16 bits of CRO.

PG (Paging, bit 31)

, ,

This bit enables paging when set and disables paging when clear. See Chapter ~ for more information about paging. See Chapter 10 for information on how to enable paging.

When an exception is generated during paging, the CR2 register has the 32-bit linear address which caused the exception. See Chapter 9 for more information about handling exceptions generated during paging (page faults).

When paging is used, the CR3 register has the 20 most-significant bits of the address of the page directory (the first-level page table). The CR3 register is also known as the page-directory base register (PDBR). Note that the page directory must be aligned to a page boundary, so the low 12 bits of the register are ignored. Unlike the Iiltel386 DX processor, the Intel486 processor assigns functions to two of these bits. These are:

PCD (Page-Level Cache Disable, bit 4 of CR3)

The state of this bit is drjven on the PCD pin during QUs cycles which are not paged, such as interrupt acknowledge cycles, when paging is enabled. It is driven during all bus cycles when paging is not enabled. The PCD pin is used to control caching ,in an external, cache on a cycle-by-cycle basis.

PWT (Page-Level Writes Transparent, bit 3 of CR3)

The state of this bit· is driven on the PWT pin during bus Cycles which are not paged, such as interrupt acknowledge cycles, when paging is enabled. It is driven during all bus cycles when paging is not enabled. The PWT pin is used to control write-through in an external cache on a cycle~by-cycle basis. '

CD (Cache Disable, bit 30)

This bit enables the internal cache when clear and disables the cache when set. Cache misses do not cause cache line fills when the bitis set. Note that cache hits are not 9isabled; to completely disable the cache, the cache must be flushed. See Chapter 12 for information on caching.

NW (Not Write-through, bit 29)

This bit enables write-throughs and cache invalidation cycles when cle,ar and disables invalidation cycles and write-throughs which hit in the cache when set. See Chapter 12 for information on caching., Disabling write-throughs can allow stale data to appear in the cache.

SYSTEM ARCHITECTURE

AM (Alignment Mask, bit 18)

This bit allows alignment checking when set and disables alignment checking when clear.

Alignment cJtecking is performed only when the AM bit is set, the AC flag is set, and the CPL.is 3 (user mode).

WP (Write Protect, bit 16)

When set, this bit write-protects user-level pages against supervisor-level writes. When this bit is clear, read-only user-level pages can be written by a supervisor process. This feature is useful for implementing the copy-on-write method of creating a new process (forking) used by some operating systems, such as UNIX.

NE (Numeric Error, bit 5)

This bit enables the standard mechanism for reporting floating-point numeric errors when set. When NE is clear and the IGNNE# input is active, numeric errors are ignored. When the NE bit is clear and the IGNNE# input is inactive, a numeric error causes the processor to stop and wait for an interrupt. The interrupt is generated by using the FERR# pin to drive an input to the interrupt controller (the FERR# pin emulates the ERROR# pin of the Intel287™ and Intel387 DX coprocessors). The NE bit, IGNNE# pin, and FERR# pin are used with external logic to implement PC-style error reporting.

ET (Extension Type;bit 4)

This bit is one to indicate support of Intel387 DX math coprocessor instructions (Intel reserved).

TS (Task Switched, bit 3)

The processor sets the TS bit with every task switch and tests it when interpreting floating-point arithmetic instructions. This bit allows delaying save/restore of numeric content until the numeric data is actually used. The CLTS instruction will clear this bit.

EM (Emulation, bit 2)

When the EM bit is set, execution of a numeric instruction generates the coprocessor-not-available exception. The EM bit must be set in the Intel486 SX microprocessor.

MP (Math Present, bit 1)

On the 286 and Intel386 DX processors, the MP bit controls the function of the WAIT instruction, which is used to synchronize with a coprocessor. When running 286 and Intel386 DX programs on processors with the Intel486 FPU, this bit should be set. The MP bit should be reset in the Intel486 SX Cpu.

intet

PE (Protection Enable, bit 0)

Setting the PE bit enables segment-level protection. See Chapter 6 for more information about protection. See Chaptf;r 10 and Chapter 22 for information on how to enable

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