MEMORY ADDRESSING

Memory is organized in sets of segments. Each seg-ment consists of a linear sequence of up to 64K bytes. These bytes are stored sequentially from byte 00000 to byte FFFFF hex. The memory is addressed using a two-compomint address (a pointer) that con-sists of a 16-bit segment base (specifying the begin-ning address of the segment in memory) and a 16-bit offset (specifying the address relative to the beginning of the segment). The base values are con-tained in one of the four internal segment registers

I

l~bb~i1s

15

EGMENT REGISTER SEGMENT

j-..l-_ _ ...JADDRESS

19

o

20-BIT

PHYSICAL MEMORY ADDRESS

Figure 2·11 Memory Addressing

2-7 seg-ment register points to the base of the stack, the data segment register points to the base of one data area, and the extra segment register points to the base of another area where data may be stored.

CONTENTS OF SEGMENT REGISTERS POINT TO THE BASE ADDRESS OF THE CORRESPONDING AREAS IN MEMORY.

Figure 2·12 Segment Registers

CODE

Figure 2·13 How an Address Is Built

Generating Addresses

Each time the CPU needs to generate a memory address, one of the s'egment registers is automatical-ly chosen and its contents added to a logical address.

For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the contents of the instruction pointer) to com-pute the value of the instruction address.

For an instruction referencing the stack, the stack segment register is automatically added to the logical address (the SP or BP register contents) to compute the value of the stack address.

For a data reference operation, where either the data or extra segment register are chosen as the base, the logical address can be made up of many different though provisions do exist to override this selection.

Since logical addresses are 16-bits wide, up to 64K (65,536) bytes in a given segment may be addressed without changing the value of the segment base register. In systems that use 64K or fewer bytes of memory for each memory area (code, stack, data and extra), the segment registers can be initialized to zero at the beginning of the program and then ignored, since zero plus a 16-bit offset yields a 16-bit address. In a system where the total amount of memory is 64K bytes or less, it is possible to set all segment registers equal and have fully overlapping segments.

Segment registers are also very useful for large pro-gramming tasks, which require isolation of program code from the data area, or isolation of module data from the stack information, etc.

Segmentation makes it easy to build relocatable and reentrant programs. In many cases, the task of relocating a program (relocation means having the ability to run lne same program in several different areas of memory without changing addresses in the program itselO simply requires moving the program code and then adjusting the code segment register to point to the base of the new code area. Since pro-grams can be written for the 8086,88 or 80186,188 in which all branches and jumps are relative to the in-struction pointer, it does not matter what value is kept in the code segment register.

Figure 2-14 shows how an entire process, consisting of code, stack and data areas, can be reloc~ted.

Likewise, in a reentrant program, a single program uses multiple data areas. Before the reentrant code is entered the second time, the data segment register value is changed so that a different data area is made available to the program.

Addressing Modes

The 8086,88 and 80186,188 provide 24 different addressing modes. Various logical address combina-tions are shown in Figure 2-15, from the simplest im-mediate data mode to the register addressing mode, where a selected register contains the data being

Exactly how the 8086,88 and 80186,188 select an ad-dressing mode for a given instruction is encoded within the bits of the instruction code. This is' de-scribed in more detail in Chapter 3.

2.4 INTERRUPTS

The interrupt system of the 8086,88 and 80186,188 is simple but versatile. Interrupts may be triggered by devices external to the CPU or by software inter-rupt instructions or, under certain conditions, by the CPU itself.

Every interrupt is assigned a type code that identifies it to the CPU. The type code is used by the CPU to point to a location in the memory based interrupt vector table containing the address of the interrupt routine. This interrupt vector table can contain up to 256 vectors for different interrupt types.

Interrupts 0-31 are reserved by Intel

The following sections provide a general introduc-tion to interrupt processing for the 8086,88 and 80186,188 CPUs. For more detailed information, see Chapter 4, Section 4.3 (8086,88) and Chapter 5, Section 5.4 (80186,188).

MODE IMMEDIATE REGISTER DIRECT

CODE CODE

STACK STACK

DATA DATA

EXTRA EXTRA

TO RELOCATE AN ENTIRE PROCESS MOVE THE CODE, STACK, AND DATA, AND UPDATE THE SEGMENT REGISTER CONTENTS TO POINT TO THE NEW AREAS.

Figure 2-14 Process Relocation

LOCATION OF OATA WITHIN INSTRUCTION

IN REGISTER

AT MEMORY LOCATION POINTED TO BY ADDRESS CONTAINED IN INSTRUCTION.

REGISTER INDIRECT AT MEMORY LOCATION POINTED TO BY ADDRESS CONTAINED IN REGISTER.

INDEXED OR BASED AT MEMORY LOCATION POINTED TO BY SUM OF INDEX REGISTER OR BASE REGISTER CONTENTS AND IMMEDIATE DATA CONTAINED IN INSTRUCTION.

BASED AND INDEXED MEMORY ADDRESS IS SUM OF BASE REGISTER CONTENTS AND WITH DISPLACEMENT INDEX REGISTER CONTENTS AND IMMEDIA TE DATA

THE LOCATION OF OAT A IS REALLY THE LOGICAL ADDRESS. WHICH IS ADDED TO THE SEGMENT REGISTER VALUE TO FORM THE PHYSICAL MEMORY ADDRESS. .

Figure 2-15 iAPX 88 Addressing Modes

2-9 ²¹⁰⁹¹¹

External Interrupts

The 8086,88 have two inputs that may be used by ex-ternal devices to signal interrupts, the INTR (Interrupt Request) line, and the NMI (Non-Maskable Interrupt) line. The INTR line is usually driven by a PIC, such as Intel's 8259A Programma-ble Interrupt. Controller, which in turn is connected to the devices that need interrupt service.

The 80186,188 have five inputs for use by external devices to signal interrupt requests: the four INT lines (INTO-INT3) and the NMI line. Two of the INT lines may function as dedicated interrupt ac-knowledge outputs. This capability is included to allow external expansion of the PIC using multiple 8259As (see Chapter 5, Section 5.10, for a detailed discussion of this facility).

On both the 8086,88 and 80186,188 CPUs, the NMI input line is generally used to signal the CPU of a

"catastrophic" event, such as imminent loss of power, memory error, or bus parity error. Interrupt requests arriving on the NMI caimot be disabled.

They are latched by the CPU, and have higher priori-ty than an interrupt request on INTR or INTO-3.

Internal Interrupts

Internal interrupts are generated by two instructions (INT and INTO), by conditions resulting from the execution of two instructions (DIV, IDIV), and by most instructions when the Single Step flag in the Flags or Status Word register is set. In addition to all these, the 80186,188 provide interrupts generated by the integrated peripherals (see Section 2.6), by two instructions (ESC and BOUND) and by the oc-currence of undefined opcodes.

A detailed discussion of interrupts is included in Chapters 4 and 5, which deal with the 8086,88 and the 80186,188 respectively, as well as in Volume 2 of this set, which covers the hardware details of inter-rupts for both CPUs.

2.5 MINIMUM AND MAXIMUM MODES