BASE
Instruction Fetch CS
Stack Operation SS
Variable (exectp following) OS
String Souce OS
String Destination ES
BP Used AS Base Register SS
BX Used As Base Register OS
Instructions are always fetched from the current code segment. The instruction pointer OP) contains the offset of the target instruction from the begin-ning of the segment.
Stack instructions always operate on the current stack segment. The stack pointer (SP) contains the offset of the top of the stack. Most variables (memory operands) are assumed to reside in the current data segment, although a program can in-struct the BIU to access a variable in one of the other currently addressable segments. The offset of a memory variable is calculated by the EU. This calcu-lation is based on the addressing mode specified in the instruction; the result of the calculation is called the operand's effective address (EA). Section 3.6 covers addressing modes and effective address calcu-lation in detail.
Strings are addressed differently from other variables. The source operand of a string instruction is assumed to lie in the current data segment, but another currently addressable segment may be specified. Its offset is taken from register SI, the source index register. The destination operand of a string instruction always resides in the current extra segment (ES). Its offset is taken from the DI, the destination index register. The string instructions au-tomatically adjust SI and DI as they process the strings one byte or word at a time.
When register BP, the base pointer register, is designated as a base register in an instruction, the variable is assumed to reside in the current stack segment. Register BP thus provides a convenient way to address data on the stack. BP can be used, however, to access data in any of the other currently addressable segments.
In most cases, the BIU's segment assumptions are a convenience to the programmer, since they are
CS, ES, SS Effective Address CS, ES,SS SI
NONE 01
CS, OS, ES Effective Address CS, ES, SS Effective Address
based on the most frequent typical usage. It is possible, however, to explicitly direct the BIU to access a variable in any of the currently addressable segments (the only exception is the destination oper-and of a string instruction which must pe in the extra segment). This is done by preceding an instruction that are position-independent, or dynamically relocatable. Dynamic relocation allows a multi-programming or multitasking system to make partic-ularly effective use of the available memory. Inactive programs can be written to disk, and the space they occupied allocated to other programs. If a disk-resident program is needed lat<:r, it can be read back into any available memory location and restarted.
Similarly, if a program needs a large contiguous block of storage, and the total amount is available only in nonadjacent fragments, other program seg-ments can be compacted to free up a continuous space. This process is shown graphically in Figure 3-14.
In order to be dynamically relocatable, a program must not load or alter its segment registers and must not transfer directly to a location ou tside the current code segment. In other words, all offsets in the
BEFORE RELOCATION AFTER RELOCATION
Figure 3-14 Dynamic Code Relocation
Stack Implementation
Stacks are located in memory and are accessed by the stack segment register (SS) and the stack pointer register (SP). A system may have an unlimited generally referred to simply as the stack. SS contains the base address of this stack and SP points to the top of the stack (TOS). In other words, SP contains the offset of the top of the stack from the stack seg-ment's base address. The stack's base address (contained in SS), however, is not the bottom of the stack.
Stacks are 16-bits wide; thus, instructions that oper-ate on stacks add and remove stack items one word to-wards its base address. Stack operations never move items on the stack, nor do they erase them. The top of the stack changes only as a result of updating the stack pointer.
Dedicated and Reserved Memory
Locations . processing. Application systems should not use these areas for any other purpose. Doing so may make these systems incompatible with future Intel products.
As Figure 3-16 indicates, the 8086,88 and the 80186,188 processors differ in the proportion of dedicated to reserved locations.
EXISTING
STACK OPERATION FOR CODE SE~UENCE PUSH AX
POPAX POP BX
Figure 3-15 Stack Operation
RESERVED
RESERVED FFH RESERVED
14H RESERVED F8H
13H F7H
DEDICATED OPEN DEDICATED
OH OH
iAPX86,88 iAPX 186,188
Figure 3-16 Reserved and Dedicated Memory and I/O Locations
FFFFH
Integrated Peripheral Control Block The 80186,188 integrated peripherals are controlled by an array of l6-bit registers located in an internal 256-byte control block. Control and status registers are provided for the chip select unit, the DMA controller, the timers, and the interrupt controller.
The control block may be mapped into memory or I/O space. The control block base address is pro-grammed by the 16-bit relocation register, which is contained in the control block itself. Each of the con-trol and status registers are located at a fixed offset from the base address.
8086/80186 and 8088/801 88 Memory Access Differences
The 8086 and 80186 can access either 8 or 16 bits of memory at a time. If an instruction refers to a word variable, and that variable is located at an even-numbered address, the 8086/80186 accesses the complete word in one bus cycle. If the word is located at an odd-numbered address, it is accessed one byte at a time in two consecutive bus cycles.
Thus, to maXImIze throughput in 8086- and 80186-based systems, 16-bit data should be stored at even addresses (i.e., it should be word aligned). This is parttcularly true of stacks. Unaligned stacks can slow a system's response to interrupts. Neverthe-less, except for the performance penalty, word align-ment is totally transparent to software, allowing maximum data packing where memory space is constrained.
The 8086/80186 always fetch the instruction stream in words from even addresses, except that the first fetch after a program transfer to an odd address 0 b-tains a byte. The instruction stream is disassembled inside the processor, and instruction alignment will not materially affect the performance of most systems.
The 8088 and 80188 always access memory in bytes.
Word operands are accessed in two bus cycles regardless of their alignment. Instructions are also fetched one byte at a time. Although alignment of word operands does not affect the performance of the 8088/188, locating 16-bit data on even addresses will insure maximum throughput if the system is ever transferred to an 8086 or 80186.
3.5 I/O PORT ORGANIZATION
The 8086,88 and 80186,188 have a versatile set of input/output facilities. The processors provide a large I/O space that is separate from the memory space. I/O devices may also be placed in the memory space to bring the power of the full instruction set and addressing modes to input/output processing.
For high speed transfers, the 8086,88 may be used with traditional direct memory access controllers or the 8089 I/O Processor. The 80186,188 has an in-tegrated DMA controller with two high-speed DMA channels. so that words will be transferred in a single bus cycle.
An 8-bit device may be located at either an even or odd address. Thus, internal registers in a given 8-bit device will have all even or all odd addresses.
To access a port, the BIU places the port address (O-FFFFH) on the lower 16 lines of the address bus.
Different forms of the I/O instructions allow the ad-dress to be specified as a fixed value in the
The first 256 ports are directly addressable (address in the instruction) by some input/output instruc-tions; other instructions let the programmer address the total of 64K ports indirectly (address in a register) .
Restricted I/O Locations
As shown in Figure 3-16, on both the 8086,88 and 80186,188 processors, locations F8H throughFFH (eight of the 64K locations) in the I/O space are re-served by Intel Corporation for use by future Intel hardware and software products. Using these loca-tions for any other purpose may inhibit compatibility with future Intel products. Locations FFFE and FFFF are dedicated, on the 80186,188 processors, to the relocation register's reset location. On the 8086,88 these locations are reserved.
Memory-Mapped 1/0
I/O devices may also be placed in the memory space.
This memory-mapped I/O provides additional pro-gramming flexibility. Any instruction that references memory may be used to access an 110 port located in the memory space. A group of terminals, for example, could be treated as an array in memory, with an index register selecting one of the terminals in the array.
Memory reference instructions take longer to execute, however, and are less compact than the simpler IN and OUT instructions.
3.6 ADDRESSING MODES
The 8086,88 and 80186,188 provide many different ways of addressing operands. Operands may be con-tained in registers, within the instruction itself, in memory or in I/O ports. In addition, the addresses of memory and 110 port operands can be calculated in several different ways. These addressing modes greatly extend the flexibility and convenience of the instruction set.
Register and Immediate Operands
Instructions that specify only register operands are generally the most compact and fastest executing.
This is because the register addresses are encoded in instructions in just a few bits, and because these op-erations are performed entirely within the CPU (no bus cycles are run). Registers may serve as source operands, destination operands, or both.
Immediate operands are constant data contained in an instruction. The data may be either 8 or 16 bits long. Immediate operands can be accessed quickly because they are available directly from the instruc-tion queue; (as in the case of register operands, no bus cycles need to be run to obtain an immediate operand). The limitations of immediate operands are that they may only serve as source operands and that they are constant values.
Memory Addressing Modes
Unlike register and immediate operands, which are directly accessible to the EU, memory operands must be transferred to and from the CPU over the bus. When the EU needs to read or write a memory
operand, it must pass an offset value to the BIU. The BIU adds the offset to the (shifted) contents of a seg-ment register, producing a 20-bit physical address, and then executes the bus cycle(s) needed to access the operand.
The Effective Address
The offset that the EU calculates for a memory oper-and is called the operoper-and's effective address or EA.
It is an unsigned 16-bit number that expresses the operand's distance in bytes from the beginning of the segment in which it resides. The EU can calculate the effective address in several different ways. Infor-mation encoded in the second byte of the instruction tells the EU how to calculate the effective address of each memory operand. A compiler or assembler derives this information from the statement or in-struction written by the programmer. Assembly lan-guage programmers have access to all addressing modes.
As shown in Figure 3-17, the EU calculates the EA by summing a displacement, the contents of a base register, and the contents of an index register. The fact that any combination of these three components may be present in a given instruction results in the great variety of memory addressing modes provided by the 8086,88 and 80186,188.
The displacement element is an 8- or 16-bit number that is contained in the instruction. The displacement generally is derived from the position of the operand name (a variable or label) in the program. The pro-grammer can also modify this value or specify the displacement explicitly.
A programmer may specify that either BX or BP is to serve as a base register whose contents are to be used in the EA computation. Similarly, either SI or DI may be specified as an index register. Whereas the displacement value is a constant, the contents of the base and index registers may change during the execution. This makes it possible for one instruction to access different memory locations as determined by the current value in the base and/or ind·ex registers.
Effective address calculations with the BP are made, by default, using the SS register, though either the DS or the ES registers may be specified instead.
3-15
ENCODED INTHE INSTRUCTION
EXPLICIT { INTHE INSTRUCTION
ASSUMED UNLESS OVERRIDDEN BY PREFIX
SINGLE INDEX DOUBLE INDEX
~
ORX.
j d b S I ORBP· 01
i
EFFECTIVEr- - / ADDRESS
+ ~I:':LA:CEMENT
l----
+EU
l
BIUFigure 3-17 Memory Address Computation