DMA CHANNELS

to one channel over the other, or they may be pro-grammed to alternate cycles when both have DMA requests pending.

2-11

Timers

The 80186,188 include three internal 16-bit pro-grammable timers. Two of these are highly flexible and are connected to external pins. They can be used to count external events, time external events, generate nonrepetitive waveforms, etc. The third timer is not connected to external pins, and is useful for real-time coding and time delays.

The timers are controlled by eleven 16-bit registers in the internal peripheral control block. A timer mode/control register within this block allows the user to program the specific mode of operation or

internal interrupt controller serves to merge these requests on a priority basis, for individual service by the CPU.

The interrupt controller has its own control registers,used to set the mode of operation for the controller. Internal interrupt sources can be disabled by their own control registers or by mask bits from the interrupt controller.

The interrupt controller resolves priority among simultaneously pending requests. Nesting is permitted, i.e., interrupt service routines may be in-terrupted by those of equal or higher priority.

If interrupts are undesirable, the controller may be used in a polled mode. When polling, the processor disables interrupts and then simply polls the inter-rupt controller (rather than the individual interinter-rupt sources) whenever it is convenient.

Clock Generator

The on-chip clock generator provides both internal and external clock generation. It includes a crystal oscillator, a divide-by-two counter, synchronous and asynchronous ready inputs, and reset circuitry.

The oscillator circuit is designed to operate with a parallel resonant fundamental mode crystal. The crystal frequency is double the CPU clock frequency.

An external oscillator may be used instead of the

The 8087 Numeric Processor Extension (NPX) per-forms arithmetic and comparison operations (using 80-bit internal registers) on a variety of numeric data types. It also executes numerous built-in tran-scendental functions such as log, tangent, etc. In con-junction with the maximum mode 8086,88 CPUs, or the 80186,188 CPUs, the NPX effectively extends the register and instruction sets of the host CPU and adds several new data types as well. The 8087 block diagram is shown in Figure 2-17.

The 8087 uses the standard iAPX 86/186 family in-struction set plus over fifty numeric inin-structions.

Programs can be written in ASM-86 assembly language, or in the Intel high-level languages PLlM-86, Fortran-86 and Pascal-86. From the stand-point of the programmer the NPX is not perceived as a separate device; instead, the computational abili-ties of the CPU appear greatly expanded.

The 8087 adds extensive high-speed numeric pro-cessing capabilities to the CPU. It conforms to the IEEE format for single- and double-precisiOri floating point numbers. Even for programmers who are not expert in the problems of numerical analysis (for instance, the accumulation of rounding errors which may result from a long chain of floating point calculations), the 8087 will provide correct results, and is straightforward and easy to program. Chapter 6 of this volume describes the software aspects of the 8087; Chapter 3 of Volume 2 covers the hardware.

NUMERIC DATA PROCESSOR (8087)

BUS INTER FACE UNIT I flOATING POINT EXECUTION UNIT

I

j

INSTRUCTIONS CONTROL

J

UNIT

Figure 2-17 Numeric Data Processor Block Diagram

2.8 THE 8089 1/0 PROCESSOR (lOP) The 8089 Input/Output Processor is a high-performance, general purpose I/O system on a chip (see Figure 2-18). It is an independent microproces-sor that optimizes input/output operations. It is de-signed to remove all I/O details from applications to provide a powerful I/O subsystem. I/O subsystem changes or upgrades can be made without impact to application software.

The CPU communicates with the lOP in two modes:

initialization and command. The lOP has two inde-pendent channels, each with its own register set, channel attention, interrupt request and DMA con-trol signals.

Programs are written in ASM-89, the 8089 assembly language. About 50 basic instructions are available, including general purpose instructions similar to those found in CPU s as well as instructions specifi-cally tailored for I/O operations.

In the case of the 80186,188 and 8089 combination, the 8089 is used in the remote mode only. This is de-scribed in Chapter 7 of this manual; hardware con-siderations are in Volume 2, Chapter 4.

HOST CPU (8086 or 8088) EXECUTION I BASE

2.9 THE 80130 OPERATING SYSTEM FIRMWARE (OSF)

The 80130 firmware (software in silicon) is, in con-junction with the 8086,88 or 80186,188 CPUs, the nucleus of a real-time, high-performance multitask-ing operatmultitask-ing system. The 80130 adds task management, interrupt management, message passing, synchronization and memory allocation capabilities to the CPU. A block diagram of the OSF is shown in Figure 2-19.

The 80130 OSF has five operating system data types:

jobs, tasks, segments, mailboxes and regions. To create, manipulate and delete these data types, the 80130 uses 35 operating-system instructions or primitives. Programs using the 80130 primitives may be written in ASM-86, PLlM-86, Fortran-86 or Pascal-86.

The OSF contains a 16-bit operating-system, a pro-grammable interrupt controller, delay timers, and a variable baud-rate generator, thus replacing about 10 LSI ICs in a system. It is connected directly to the dynamically. The design approach used in the 80130 OSF is one common to mini and mainframe

PUBLIC MEMORY CHANNEL 1 PROGRAM

PROGRAM

CHANNEL 2 PROGRAM DATA

Figure 2-18 1/0 Processor Block Diagram 2-13

HOST CPU (8086,88,186,188)

r-l

EXECUTION UNIT BUS CONTROL LOGIC

INTERFACE UNIT

UNIT

A ...A

ADDR/DATA BUS

.. _"

I--...A

H

^L

A TIMER

STATUS/CONTROL BUS I

SYSTEM

..

H

^L