INTRODUCTION 3.2 CPU ARCHITECTURE This chapter describes the programmer's

architec-ture of the iAPX 86,88 and iAPX 186,188 CPUs. It is divided into the following sections:

The two independently operating functional units of the CPU, the BIU and EU, are able, under most circumstances, to extensively overlap instruction fetch with execution. The result is that, in most cases, the time normally required to fetch tions "disappears" because the EU executes instruc-tions that have already been fetched by the BIU.

Figure 3-1 illustrates this overlap and compares it with traditional microprocessor operation. In the example, overlapping reduces the elapsed time re-quired to execute three instructions, and allows two additional instructions to be pre fetched as well.

• •

1st INSTRUCTION (ALREADY FETCHED):

iii

Ia

EXECUTE AND WRITE RESULT

2nd INSTRUCTION:

EXECUTE ONLY

3rd INSTRUCTION:

READ OPERAND AND EXECUTE

4th INSTRUCTION:

(UNDEFINED)

5th INSTRUCTION:

(UNDEFINED)

Figure 3-1 Overlapped Instruction Fetch and Execution 3-1

Execution Unit

In the execution unit, a 16-bit ALD maintains the CPD status and control flags, and manipulates the general registers and instruction operands. All regis-ters and data paths within the ED are 16 bits wide (Figure 3-2).

The ED has no connection to the system bus, the

"outside world." It obtains instructions from a queue maintained by the BID. Likewise, when an in-struction requires access to memory or to a peripher-al device, the ED requests the BID to fetch or store the data. All addresses manipulated by the ED are 16 bits wide. However, the address relocation facility provided by the BID provides the ED with access to a full megabyte of memory space.

A

,...

I

EXECUTION UNIT (EU)

GENERAL functionally identical, but are implemented different-ly to match the data path size of their buses, which are 8 bits and 16 bits respectively.

The BID performs all bus operations for the ED.

Data is transferred between the CPD and memory or I/O devices upon demand from the ED.

In addition, during periods when the ED is busy ex-ecuting instructions, the BID "looks ahead" and fetches more instructions from memory. The in-structions are stored in an internal RAM array called the instruction stream queue. The 8088/80188 in-struction queue holds up to four bytes of the instruc-tion stream, while the 8086/80186 queue can store up to six instruction bytes. These queue sizes keep the ED supplied with prefetched instructions under most conditions without monopolizing the system bus.

BUS INTERFACE UNIT (BIU)

SEGMENT

Figure 3-2 Execution and Bus Interface Units (EU and BIU)

The 8088/80188 BIU fetches another instruction byte whenever there is one empty byte in its queue, and there is no active request for bus access from the EU. The 8086/80186 BIU operates similarly except that it does not normally initiate a fetch until there are two empty bytes in its queue.

The 8086/80186 BIU will generally obtain two in-struction bytes per fetch; if a program transfer forces fetching from an odd address, the BIU automatically reads one byte from the odd address and then resumes fetching two-byte words from the subse-quent even address.

Under most circumstances, the queue contains at least one byte of the instruction stream, and the EU does not have to wait for instructions to be fetched.

The instructions in the queue are those stored in the memory locations immediately adjacent to and higher than the instruction currently being executed. That is, they are the next logical instruc-tions so long as execution proceeds serially. If the EU executes an instruction that transfers control to another location, the BIU fetches the instruction from the new address, passes it immediately to the EU, and then begins refilling the queue from the new location (no flushing of the previous contents is necessary). In addition, the BIU suspends instruction fetching whenever the EU requests a memory or I/O read or write (except that a fetch already in progress is completed before executing the EU's bus request).

3_3 REGISTER STRUCTURE

The 8086,88 and 80186,188 contain the same basic set of fourteen registers as shown in Figure 3-3.

These registers are grouped into the following categories: general registers, segment registers, and status and control registers.

General Registers

The CPUs have eight 16-bit general registers. They are divided into two files of four registers each: the data register file and the pointer and index register file.

The upper and lower halves of the data registers are separately addressable. This means that each data register can be used interchangeably as a 16-bit register, or as two 8-bit registers.

The 16-bit data registers are named AX, BX, CX, and logic operations. Some instructions (e.g. string instructions), however, require certain general regis-ters for specific uses (see Table 3-1). This implicit register use allows a more compact instruction encoding.

Table 3-1 Implicit Use of General Register

REGISTER OPERATIONS

AX Word Multiply, Word Divide, Word I/O

AL Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal Arithmetic

AH Byte Multiply, Byte Divide BP Enter, Leave (186, 188 only) BX Translate

CX String Operations CL Variable Shift and Rotate DX Word Multiply, Word Divide,

Indirect I/O SP Stack Operations

SI String Operations DI String Operations

The pointer and index registers consist of the 16-bit registers SP, BP, SI, and DI as shown in Figure 3-3.

They can also be used in most arithmetic and logic operations. These registers usually contain offset ad-dresses for addressing within a segment. They reduce program size by eliminating the need for each instruction to specify frequently used addresses. These registers serve another function;

they provide for dynamic logical address computa-tion as described in the seccomputa-tion on operand addressing. The pointer and index registers are also used implicitly in some instructions (Table 3-1).

As shown in Figure 3-3, this register file is divided into the pointer subfile (SP and BP) and the index subfile (SI and DO. The pointer registers provide convenient access to the current stack segment (as opposed to the data segment). Unless otherwise specified in the instruction, pointer registers refer to the current stack segment while index registers refer to the current data segment. In certain instances, specific uses of these four registers are indicated by the mnemonic phrases "stack pointer," "base pointer," "source index," and "destination index."

AX BX CX OX

SP BP SI 01

CS OS SS ES

IP STATUS WORD OR FLAGS

DATA REGISTERS

7 07

o

AH AL

BH BL

CH CL

DH DL

POINTER AND INDEX REGISTERS

15 0

I I

SEGMENT REGISTERS

15 0

I I

INSTRUCTION POINTER AND FLAGS

15 0

I

pi

I

15 11 10 9 8 7 6 5 4 3 2 1 0

Figure 3-3 Register Structure

STACK POINTER BASE POINTER SOURCE INDEX DESTINATION INDEX

CODE DATA STACK EXTRA

INSTRUCTION POINTER

Segment Registers

The segment registers are also 16-bit registers.

These registers specify the four currently addressable memory segments: CS (code segment), DS (data segment), SS (stack segment), and ES (extra segment). All instructions are fetched from the cur-rent code segment, offset by the instruction pointer OP) register. Operand fetches are usually made from the current data segment (DS) or the current stack segment (SS), depending on whether the offset ad-dress was calculated from the contents of a pointer register. For the exceptional cases where operand references are required outside the default segment, a segment override prefix may be added to the in-struction to designate the required segment.

Status and Control Registers

The status and control registers consist of the in-struction pointer and the status word or flags.

The 16-bit instruction pointer OP) is analogous to the program counter (PC) in earlier CPU sand points to the next instruction. The instruction point-er is updated by the BIU so that it contains the offset ad-dress of a relative jump.

STATUS FLAGS

The status word or flags is a 16-bit register consisting of three control flags and six status flags (see Figure 3-4). The status flags record specific characteristics of the result of logical and arithmetic instructions (bits 8,9, and 10); the six status flags control the op-eration of the CPU within a given operating mode (bits 0, 2, 4, 6, 7, and 11).

The status flags provide status information that the EU posts to reflect certain properties of the result of an arithmetic or logic operation. A group of instruc-tions is available that allows a program to alter its ex-ecution depending on the contents of the status flags, that is, on the result of a prior operation. Table 3-2 summarizes the status word or flag bit functions.

Different instructions affect the status flags differently; in general, however, the flags reflect the used by decimal arithmetic instructions.

2) If CF (carry flag) is set, there has been a carry out of, or a borrow into, the high-order bit of the result (8- or 16-bit). The flag is used by instructions that add and subtract multibyte numbers. Rotate in-structions can also isolate a bit in memory or a regis-ter by placing it in the carry flag.

CARRY - - - , PARITY - - - , AUXILIARY CARAY - - - ' - - - ,

L -_ _ _ _ _ _ _ _ _ DIRECTION FLAG

~ INTEL RESERVED

Figure 3-4 Status Word or Flags Format 3-5

Bit

Table 3-2 Status Word or Flags Bit Functions

Position ^Name Function

0 CF Carry Flag-Set on high-order bit carry or borrow; cleared otherwise 2 PF Parity Flag-Set if low-order 8 bits of result contain an even number bf 1-bits; cleared otherwise

7 SF Sign Flag-Set equal to high-order bitofresult(Oifpositive, 1 if negative) 8 TF Single Step Flag-Once set, a sin-gle step interrupt occurs after the next instruction executes. TF is cleared by the single step interrupt.

9 IF Interrupt-enable Flag-When set, maskable interrupts will cause the CPU to transfer control to an inter-rupt vector specified location.

10 DF Di rection Flag-Causes string instructions to auto decrement the appropriate index register when set. Clearing DF causes auto increment.

11 OF Overflow Flag-Set if the signed result cannot be expressed within the number of bits in the destination operand; cleared otherwise

3) If OF (the overflow flag) is set, an arithmetic overflow has occurred; that is, a significant digit has been lost because the size of the computation ex-ceeded the capacity of its destination location. An op-tional Interrupt On Overflow instruction is available that generates an interrupt in this situation.

4) If SF (the sign flag) is set, the high-order bit of

th~ result is a 1. Since negative binary numbers are represented by standard two's complement notation, SF indicates the sign of the result

The three control flags are used by programs to alter processor operations in specified ways. The direction

flag controls the direction of the string manIpula-tions, the interrupt flag enables or disables external interrupts, and the trap flag puts the processor into a single-step mode for debugging.

The control flags are set and cleared as follows:

]) Setting DF (the direction flag) causes string in-structions to auto-decrement, that is, to process strings from high addresses to low addresses, or from right to left. Clearing DF causes string instruc-tions to auto-increment, or to process strings from left to right.

2) Setting IF (the interrupt-enable flag) allows the CPU to recognize maskable, external interrupt requests (including interrupts from 80186,188 tegrated peripherals). Clearing IF disables these in-terrupts. IF has no effect on either nonmaskable external or internally generated interrupts.

3) Setting TF (the trap flag) puts the processor into single-step mode for debugging. In this mode, the CPU automatically generates an internal interrupt after each instruction, allowing a program to be in-spected as it executes, instruction by instruction.