H X
BI (0-8) X L H X
AOo = Previous AO before H-to-L transition of ALE BOo = Previous BO before H-to-L transition of BLE
Logic Diagram
ALE or BLE
AO (0-8)
Z L H AOo
BO(0-8)
Z L H BOo
Functional Description
The SCAN18373T consists of two sets of nine D-type latch-es with TRI-ST ATE standard outputs. When the Latch En-able (ALE or BLE) input is HIGH, data on the inputs (AI(0-8) or BI(0-8) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The TRI-STATE standard outputs are con-trolled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard out-puts are in the high impedance mode, but this does not interfere with entering new data into the latches.
AOEt or BOEt
ADO or BOO AOt or BOt A02 or B02 A03 or B03 AD, or B04 A05 or B05 A06 or B06 Ao., or Bo., ADa or BOa TLIF/10962-13 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
ALE
AI [0-8]
TOI
TMS
TCK
BI [0-8]
BlE
BOE1
TYPEl
TO BSR [41]
TEST ACCESS
PORT (TAP)
TYPEl
TYPEl
Note: BSR stands for Boundary Scan Register.
Byte-A TYPE2
Tap Controller
FROM BSR [0]
BYPASS REGISTER INSTRUCTION
REGISTER
INSTRUCTION TRI-STA TE
Byte-B
TYPE2
INSTRUCTION TRI-STATE
TL/F/l0962-2
TOO
TLlF/l0962-3
BO [0-8]
TLlF/l0962-4
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are The INSTRUCTION register is an eight-bit register which one of the following two types depending upon their loca- captures the value 00111101.
tion. Scan cell TYPE1 is intended to solely observe system The two least significant bits of this captured value (01) are data, while TYPE2 has the additional ability to control sys- required by IEEE Std 1149.1. The upper six bits are unique tem data. (See I EEE Standard 1149.1 Figure 10-11 for a to the SCAN 18373T device. SCAN CMOS Test Access Log-further description of scan cell TYPE1 and Figure 10-12 for ic devices do not include the IEEE 1149.1 optional identifi-a further description of scidentifi-an cell TYPE2.) cation register. Therefore, this unique captured value can be Scan cell TYPE1 is located on each system input pin while used as a "pseudo ID" code to confirm that the correct scan cell TYPE2 is located at each system output pin as device is placed in the appropriate location in the boundary well as at each of the two internal active-high output enable scan chain.
signals. AOE controls the activity of the A-outputs while Instruction Register Scan Chain Definition BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage iden- TOI TOO
tical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition Logic 0
IotSB
MSB --+ LSB Instruction Code
00000000
LSB TLlF/10962-10
Instruction EXTEST
10000001 SAMPLE/PRELOAD
TL/F/10962-9
Scan Cell TYPE1
10000010 00000011 All Others
SCAN OUT (to next cell)
DATA IN
---r---t---
DATA OUTSHIFT _OR ----+---1
SCAN IN (from previous cell)
CLOCK-OR
Scan Cell TYPE2
SCAN OUT (to next cell)
IotOOE
---I
DATA I N - -...
---+---I
CLAMP HIGHZ BYPASS
TL/F/10962-7
DATA OUT
Description of Boundary-Scan Circuitry
(Continued) Boundary-Scan Register Scan Chain Definition (42 Bits In Length)TOI
41
40
39
38
37
36
35 18 17
34 19 16
33 20 15
32 21 14
31 22 13
30 23 12
29 24 11
28 25 10
27 26
TOO
TLlF/10962-25
Description of Boundary-Scan Circuitry
(Continued) Boundary-Scan Register Definition IndexBit No. Pin Name Pin No. Pin Type Scan Cell Type
41 AOE1 3 Input TYPE1
40 ACP 54 Input TYPE1
39 AOE Internal TYPE2 Control
38 BOE1 26 Input TYPE1 Signals
37 BCP 31 Input TYPE1
36 BOE Internal TYPE2
35 Ala 55 Input TYPE1
34 AI1 53 Input TYPE1
33 AI2 52 Input TYPE1
32 AI3 50 Input TYPE1
31 AI4 49 Input TYPE1 A-in
30 Ais 47 Input TYPE1
29 Ais 46 Input TYPE1
28 AI7 44 Input TYPE1
27 Ala 43 Input TYPE1
26 Blo 42 Input TYPE1
25 BI1 41 Input TYPE1
24 BI2 39 Input TYPE1
23 BI3 38 Input TYPE1
22 BI4 36 Input TYPE1 B-in
21 Bis 35 Input TYPE1
20 Bis 33 Input TYPE1
19 BI7 32 Input TYPE1
18 Bla 30 Input TYPE1
17 AOo 2 Output TYPE2
16 A01 4 Output TYPE2
15 A02 5 Output TYPE2
14 A03 7 Output TYPE2
13 A04 8 Output TYPE2 A-out
12 AOs 10 Output TYPE2
11 AOs 11 Output TYPE2
10 A07 13 Output TYPE2
9 AOa 14 Output TYPE2
8 BOo 15 Output TYPE2
7 B01 16 Output TYPE2
6 B02 18 Output TYPE2
5 B03 19 Output TYPE2
4 B04 21 Output TYPE2 B-out
3 BOs 22 Output TYPE2
2 BOs 24 Output TYPE2
1 B07 25 Output TYPE2
0 BOa 27 Output TYPE2
Absolute Maximum Ratings
(Note 1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (Vee) -0.5V to + 7.0V
DC Input Diode Current (11K)
VI = -0.5V -20mA
VI = Vee + 0.5V +20mA
DC Output Diode Current (10K)
Vo = -0.5V -20mA
Vo = Vee + 0.5V +20mA
DC Output Voltage (Vo) -0.5V to Vee + 0.5V DC Output Source/Sink Current (10) ±70mA DC'Vee or Ground Current
Per Output Pin ±70mA
liN Maximum Input
5.5 ±0.1
Leakage Current
liN Maximum Input Leakage 5.5 2.8
TDI, TMS -385
Minimum Input Leakage 5.5 -160 10LD tMinimum Dynamic
5.5 94
10HD Output Current -40
tMaximum test duration 2.0 ms, one output loaded at a time.
Storage Temperature - 65°C to + 150°C
ESD (Min) 2000V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom-mend operation of SCANTM circuits outside databook specifications.