D Flip-Flop with TRI-STATE® Outputs - Description of Boundary Scan

General Description

The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable con-trol signals. This device is compliant with IEEE 1149.1 Stan-dard Test Access Port and BOUNDARY-SCAN Architecture with the incorporation of the defined BOUNDARY-SCAN test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).

Ordering Code:

See Section 11

Connection Diagram

\.../

TtolS- 1 56 ~TDI

AOo- 2 55 .... Alo

A0E,- 3 54 ^~ACP

Ao,- 4 53 r-AI,

A02- 5 52 r-A12

GND- 6 51 r-GND

A03- 7 50 ~All

AO.- 8 49 -AI.

vec - 9 48 -Vee

AOs- 10 47 -Als

AOs- 11 46 -Als

GND- 12 45 r-GNO

A~- 13 4<4 -A17

AOa- 14 43 ~Ala

8°0- 15 42 ~810

Bo,- 16 41 -BI,

GNO- 17 40 t-GNO

8°2- 18 39 r-812

80l - 19 38 r-81l

vec - 20 37 r-Vcc

80.- 21 36 r-81.

8°5- 22 35 -815

GNO- 23 3<4 -GNO

80s - 24 33 -81s

8~- 25 32 -817

BOE,- 26 31 -8CP

80a- 27 30 t-81a

TOO- 28 29 t-TCK

TL/F/l0963-1

Features

• IEEE 1149.1 (JTAG) Compliant

• Buffered positive edge-triggered clock

• TRI-STATE outputs for bus-oriented applications

• 9-bit data busses for parity applications

• Reduced-swing outputs source 32 rnA/sink 64 rnA (Comm), source 24 rnA/sink 48 rnA (Mil)

• Guaranteed to drive 50n transmission line to TIL input levels of 0.8V and 2.0V

• TIL compatible inputs

• 25 mil pitch SSOP (Shrink Small Outline Package)

• Includes CLAMP and HIGHZ instructions

• Member of National's SCAN Products

Pin Names AI(O-B), BI(O-B) ACP, BCP AOE1, BOE1 AO(O-B), BO(O-B)

Order Number SCAN18374TSSC SCAN 18374 TSSCX SCAN 1837 4TFMQB 5962-9320701 MXA

Description Data Inputs Clock Pulse Inputs TRI-STATE Output Enable Inputs TRI-STATE Outputs

Description SSOP in Tubes SSOP in Tape and Reel Flatpak Military Military SMD #

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^0l:Io-I

Truth Tables

Inputs ACP AOE1 AI(O-S)

X H X

....r

L L

....r

L H

Inputs BCP BOE1 BI(0-8)

X H X

....r

L L

....r

L H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance J " = L·to·H Transition

Logic Diagram

ACP or BCP

AOE, or BOE,

AO(O-S) Z L H

BO(O-S) Z L H

Functional Description

The SCAN18374 consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable pins are common to all flops. Each set of the nine flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (ACP or BCP) transition. With the Output Enable (AOE1 or BOE1) LOW, the contents of the nine flip-flops are available at the outputs. When the Output Enable is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops.

TL/F/l0963-13 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Block Diagrams

Byte-A

TYPE1 TYPE2

TYPE1

ACP

INSTRUCTION TRI-STATE

Block Diagrams

(Continued)

TDI

TMS

TCK

BI [o-a]

BCP

BOE1

Note: BSR stands for Boundary Scan Register

TO BSR[41j

TEST ACCESS

PORT (TAP)

Tap Controller

FROM BSR[Oj BYPASS

Byte-B

INSTRUCTION TRI-STATE

TOO

TLlF/l0963-3

TL/F/l0963-4

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are The INSTRUCTION register is an eight-bit register which one of the following two types depending upon their loca- captures the value 00111101.

tion. Scan cell TYPE1 is intended to solely observe system The two least significant bits of this captured value (01) are data, while TYPE2 has the additional ability to control sys- required by IEEE Std 1149.1. The upper six bits are unique tem data. (See IEEE Standard 1149.1 Figure 10-11 for a totheSCAN18374Tdevice. SCAN CMOS Test Access Log-further description of scan cell TYPE1 and Figure 10-12 for ic devices do not include the IEEE 1149.1 optional identifi-a further description of scidentifi-an cell TYPE2.) cation register. Therefore, this unique captured value can be Scan cell TYPE1 is located on each system input pin while used as a "pseudo 10" code to confirm that the correct scan cell TYPE2 is located at each system output pin as device is placed in the appropriate location in the boundary well as at each of the two internal active-high output enable scan chain.

signals. AOE controls the activity of the A-outputs while Instruction Register Scan Chain Definition BOE controls the activity of the B-outputs. Each will activate

their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage iden-tical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition LogiC 0

TOI

IoISB

MSB ---+ LSB Instruction Code

00000000

TOO

LSB TL/F/10963-10

Instruction EXTEST

10000001 SAMPLE/PRELOAD

TL/F/10963-9

Scan Cell TYPE1

10000010 00000011 All Others

SCAN OUT (to nlxt cIII)

DATA IN

---"""T"---t---

^{DATA OUT}

SHIH _DR ----+---1

SCAN IN (from previous cell)

CLOCK-DR

Scan Cell TYPE2

SCAN OUT (to next cell)

OATA I N - - . . . , . - - - f - - - t

CLAMP HIGHZ BYPASS

TLlF/10963-7

DATA OUT

.---,

Description of Boundary-Scan Circuitry

(Continued) Boundary-Scan Register Scan Chain Definition (42 Bits In Length)

TOI

35 18 17

34 19 16

33 20 15

32 21 14

31 22 13

30 23 12

29 24 11

28 25 10

27 26

TOO

TL/F/l0963-25 CD W

'"

-t

Description of Boundary-Scan Circuitry

(Continued) Boundary-Scan Register Definition Index

Bit No. Pin Name Pin No. Pin Type Scan Cell Type

41 AOE1 3 Input TYPE1

40 ACP 54 Input TYPE1

39 AOE Internal TYPE2 Control

38 BOE1 26 Input TYPE1 Signals

37 BCP 31 Input TYPE1

36 BOE Internal TYPE2

35 Alo 55 Input TYPE1

34 AI1 53 Input TYPE1

33 AI2 52 Input TYPE1

32 Ala 50 Input TYPE1

31 AI4 49 Input TYPE1 A-in

30 Ais 47 Input TYPE1

29 AI6 46 Input TYPE1

28 AI7 44 Input TYPE1

27 Ala 43 Input TYPE1

26 Blo 42 Input TYPE1

25 BI1 41 Input TYPE1

24 BI2 39 Input TYPE1

23 Bla 38 Input TYPE1

22 BI4 36 Input TYPE1 B-in

21 Bis 35 Input TYPE1

20 BI6 33 Input TYPE1

19 BI7 32 Input TYPE1

18 Bla 30 Input TYPE1

17 AOo 2 Output TYPE2

16 A01 4 Output TYPE2

15 A02 5 Output TYPE2

14 AOa 7 Output TYPE2

13 A04 8 Output TYPE2 A-out

12 AOs 10 Output TYPE2

11 A06 11 Output TYPE2

10 A07 13 Output TYPE2

9 AOa 14 Output TYPE2

8 BOo 15 Output TYPE2

7 B01 16 Output TYPE2

6 B02 18 Output TYPE2

5 BOa 19 Output TYPE2

4 B04 21 Output TYPE2 B-out

3 BOs 22 Output TYPE2

2 B06 24 Output TYPE2

1 B07 25 Output TYPE2

0 BOa 27 Output TYPE2

Absolute Maximum Ratings

^{(Note 1)}

If Military/Aerospace specified devices are required, Note 1: Absolute maximum ratings are those values beyond which damage

please contact the National Semiconductor Sales to the device may occur. The databook specifications should be met, without

Office/Distributors for availability and specifications. exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not

recom-Supply Voltage (Vee) -0.5Vto +7.0V mend operation of SCANTM circuits outside databook specifications.

DC Input Diode Current (11K)

Dans le document Description of Boundary Scan (Page 168-174)