Key Features

Key Features

Key features of the 'CSx OSPs are listed below. Where a feature is exclusive to a particular device, the device's name is enclosed within parentheses and noted after that feature.

o

3S-/S0-ns single-cycle fixed-point instruction execution time (28.6/20 MIPS)

o

Upward source-code compatible with all 'C1 x and 'C2x devices

o

RAM-based memory operation ('CSO)

o

ROM-based memory operation ('CS1)

o

^{9K x} 16-bit single-cycle on-chip program/data RAM ('CSO)

o

^{1 K x} 16-bit single-cycle on-chip program/data RAM ('CS1)

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^{3K x} 16-bit single-cycle on-chip program/data RAM ('CS3)

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^{2K x} 16-bit single-cycle on-chip boot ROM ('CSO)

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^{8K x} 16-bit single-cycle on-chip program ROM ('CS1)

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^{16K x} 16-bit single-cycle on-chip program ROM ('CS3)

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^{1056 x} 16-bit dual-access on-chip data RAM

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^{224K x} 16-bit maximum addressable external memory space (64K pro-gram, 64K data, 64K I/O, and 32K global)

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32-bit arithmetic logic unit (ALU) , 32-bit accumulator (ACC) , and 32-bit ac-cumulator buffer (ACCB)

o

16-bit parallel logic unit (PLU)

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^{16 x} 16-bit parallel multiplier with a 32-bit product capability

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Single-cycle multiply/accumulate instructions

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Eight auxiliary registers with a dedicated arithmetic unit for indirect ad-dressing

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Eleven context-switch registers (shadow registers) for storing strategic CPU-controlled registers during an interrupt service routine

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Eight-level hardware stack

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0- to 16-bit left and right data barrel-shifters and a 64-bit incremental data shifter

o

Two indirectly addressed circular buffers for circular addressing

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Single-instruction repeat and block repeat operations for program code

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Block memory move instructions for better program/data management

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Full-duplex synchronous serial port for direct communication between the 'CSx and another serial device

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Time-division multiple-access (TOM) serial port

o

Interval timer with period, control, and counter registers for software stop, start, and reset

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64K parallel I/O ports, 16 of which are memory mapped

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Sixteen software-programmable wait-state generators for program, data, and I/O memory spaces

Key Features

"H~

1.3.1 Core CPU

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Extended hold operation for concurrent external DMA

o

Four-deep pipelined operation for delayed branch, call, and return instruc-tions

o

Index-addressing mode

o

Bit-reversed index-addressing mode for radix-2 FFTs

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Divide-by-one clock option

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On-chip clock generator

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JTAG boundary scan logic (IEEE standard, 1149.1)

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On-chip scan-based emulation logic

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5-V static CMOS technology with two power-down modes

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132-pin quad flat pack package

Enhancements to the 'C5x CPU maintain source code compatibility with the 'C1x and 'C2x generations while improving performance and versatility. Im-provements include a 32-bit accumulator buffer, additional scaling capabili-ties, and a host of new instructions to exploitthe additional hardware while sup-plying a more orthogonal instruction set to the user. The new control functions include an independent parallel logic unit (PLU) for performing Boolean opera-tions and a set of context-switch registers for providing zero-latency con-text-switching capabilities to interrupt service routines (ISRs). Data manage-ment has been improved through the use of new block move instructions and memory-mapped register instructions. The 'C5x has 28 memory-mapped core-CPU registers and 16 memory-mapped I/O ports. See Chapter 3 for more details.

1.3.2 On-Chip ROM

The 'C50 features a 2K

x

16-bit on-chip, maskable, programmable ROM. This memory is used for booting from slower external ROM or EPROM of program to fast on-chip or external SRAM. ROM can be selected during reset by driving the MP/tVlC pin low. Once your program has been booted into the RAM, this boot ROM can be operationally removed from the program memory space via the MP/tVlC bit in the PMST status register. If the ROM is not selected, the 'CSO starts its execution via an off-Chip memory.

The 'C51 features an 8K

x

16-bit on-chip maskable ROM. The 'CS3 features a 16K

x

16-bit on-chip maskable ROM. You can use this memory for your spe-cified program. Once the development of the program has stabilized, submit a ROM code to Texas Instruments for implementation into your device. See Chapter 6 for more details.

Key Features

1.3.3 On-Chip Data RAM

AII'C5x devices carry a 1056 x 16-bit on-chip data RAM. This RAM can be ac-cessed twice per machine cycle (dual-access RAM). This block of memory is primarily intended to store data values but, when needed, can be used to store programs as well as data. It can be configured in one of two ways: either all 1056 x 16 bits as data memory or 544 x 16 bits as data memory with 512 x 16 bits as program memory. You can select the configuration with the CNF bit in status register ST1. See Chapter 6 for more details.

1.3.4 On-Chip Program/Data RAM

The 'C50 has a 9K x 16-bit on-chip RAM. The 'C51 has a 1 K x 16-bit on-chip RAM. This memory is software configurable as program and/or data memory space. Code can be booted from an off-chip nonvolatile memory and then ex-ecuted at full speed, once it is loaded into this RAM. See Chapter 6 for more details.

1.3.5 On-Chip Memory Security

The 'C5x generation has a maskable option to protect the contents of on-chip memories. When the related bit is set, no externally originating instruction can access the on-chip memory spaces. See Chapter 6 for more details.

1.3.6 Address-Mapped Software Wait-State Generators

Software wait-state logic is incorporated without any external hardware into 'C5xfor interfacing with slower off-chip memory and I/O devices. This circuitry consists of 16 wait-state generating circuits and is user programmable to oper-ate 0, 1, 2, 3, or 7 wait stoper-ates. For off-chip memory accesses, these wait-stoper-ate generators can be mapped on 16K-word boundaries in program memory, data memory, and to the I/O ports. See Chapter 5 for more details.

1.3.7 Parallel I/O Ports

Each 'C5x device has a total of 64K I/O ports, sixteen of which are memory-mapped in data memory space. These ports can be addressed by the IN instruction or the OUT instruction. The memory-mapped I/O ports can be accessed with any instruction that reads or writes data memory. An active-low IS signal indicates a read/write operation via an I/O port. Requiring minimal off-chip address-decoding circuits, the 'C5x can easily interface with external.

I/O devices via the I/O ports. See Chapter 5 for more details.

1.3.8 Serial I/O Ports

The 'C5x devices carry two high-speed serial ports. These serial ports are ca-pable of operating at up to one-fourth the machine cycle rate (CLKOUT1). One

Key Features

of the two circuits is a synchronous, full-duplex serial port. Its transmitter and receiver are double buffered and individually controlled by maskable external interrupt signals. Data is framed either as bytes or as words. The second circuit is a full-duplex serial port that can be configured either for synchronous or for time-division multiple-access (TOM) operations. The TOM serial port is com-monly used in multiprocessor applications. See Chapter 5 for more details.

1.3.9 Hardware Timer

The 'C5x features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one-thirty-second the machine rate of the device itself, depending upon the programmable timer's divide-down ratio. This timer can be stopped, restarted, reset, or disabled by specific status bits. See Chapter 5 for more details.

1.3.10 User-Maskable Interrupts

The 'C5x devices have four external-interrupt lines. These lines are internally latched so that asynchronous interrupt operations can be performed by the TMS320 device. Also, each device possesses five internal interrupts: the timer interrupt and four serial port interrupts. See Chapter 5 for more details.

1.3.11 JTAG Scanning Logic

1.3.12 Packages

The JTAG scanning logic circuitry is used for emulating and testing purposes only. The JTAG scan logic provides the boundary scan to and from the interfac-ing devices. Also, it can be used to test pin-to-pin continuity as well as to per-form operational tests on those peripheral devices that surround the 'C5x. It is interfaced to another internal scanning logic circuitry, which has access to all of the on-chip resources. Thus, the 'C5x can perform on-board emulation by means of the JTAG serial scan pins and the emulation-dedicated pins. See IEEE Standard 1149.1 for more details.

The 'C5x devices are packaged in a 132-pin quad flat pack package (QFP).

With consideration for the pin layout of a 'C25 package, the 'C5x package is designed to minimize printed circuit board modifications when a 'C2x-based system is upgraded to a 'C5x processing system. Signal call outs for the 'C5x appear on the same side and in the same order as those for the 'C25. See Chapter 2 for details.

Chapter 2

Dans le document TMS320C5x "TEXAS (Page 32-36)