Internal Memory Organization

This section describes the memory use of the 'C5x core and the addressing modes supported by the core.

3.4.1 Core Processor Memory-Mapped Registers

Twenty-eight core processor registers are mapped into the data memory space. These are listed in Table ~2. An additional 64 memory-mapped regis-ters are reserved in page 0 of data space. These data memory locations are reserved for memory-mapped peripheral control and I/O port registers.

Table 3-2. Core Processor Memory-Mapped Registers

Name Address Description

'C5x 'C5x

Dec Hex

-

^{0-3 0-3 Reserved}

IMR 4 4 Interrupt mask register

GREG 5 5 Global memory allocation register

IFR 6 6 Interrupt flag register

PMST 7 7 Processor mode status register

RPTC 8 8 Repeat counter register

BRCR 9 9 Block repeat counter register

PASR 10 A Block repeat program address start register PAER 11 B Block repeat program address end register TREGO 12 C Temporary register for multiplicand TREG1 13 0 Temporary register for dynamic shift count TREG2 14 E Temporary register used as bit pointer

in dynamic bit test

OBMR 15 F Dynamic bit manipulation register ARO 16 10 Auxiliary register zero

ARCR 25 19 Auxiliary register compare register CBSR1 26 1A Circular buffer 1 start address register CBER1 27 1B Circular buffer 1 end address register CBSR2 28 1C Circular buffer 2 start address register CBER2 29 10 Circular buffer 2 end address register CBCR 30 1E Circular buffer control register BMAR 31 iF Block move address register

-

^{32-79 20--4F} Memory-mapped peripheral registers. See Table 5-1.

80-95 5O-5F Memory-mapped I/O port. See Table 5-1.

Internal Memory Organization

3.4.2 Memory Addressing Modes

The 'C5x can address a total of 64K words of program memory and 96K words of data memory. Chapter 6 shows how the on-chip program and data memo-ries are mapped.

The data used as instruction operands is obtained in one of the following eight ways:

o

By the direct address bus (ORB) using the direct addressing mode (e.g., ADD 01 Oh) relative to the data memory page pointer (DP)

o

By the ORB using the memory-mapped addressing mode (that is, LAMM PMST) within data page zero

o

By the auxiliary register file bus (AFB) using the indirect addressing mode (that is, ADD *)

o

By the instruction register (IREG) in short immediate operand mode (that is, ADD #OFFh)

o

By the program counter (PC) in long immediate operand mode (that is, ADD #OFFFFh)

o

By the core CPU access of a register in register access mode (that is, APL

*+ or MPY*+)

o

By the second instruction word in long immediate address mode (that is, BLDD #TBL 1,*+)

o

By the block memory address register (BMAR) in registered block memory addressing mode (that is, BLDD *+)

In the direct addreSSing mode, the 9-bit DP pOints to one of 512 pages (1 page

= 128 words). The data memory address (dma), specified by the seven LSBs of the instruction, points to the desired word within the page. The address on the ORB is formed by concatenating the 9-bit DP with the 7 -bit dma. Figure 3-2 illustrates direct addressing mode. In the illustration, the operand is fetched from data memory space via the data bus, and the address is the concatenated value ofthe DP and the seven LSBs ofthe instruction. Note that bit 7=0 defines the addressing mode as direct.

Internal Memory Organization

Figure 3-2. Direct Addressing Mode

ADD 010h

t SHFT represents a 4-bit shift value.

Memory-mapped addressing mode operates much like direct addressing mode except that the most significant 9 bits of the address are forced to zero instead of being loaded with the contents of the DP. This allows the user to di-rectly address the memory-mapped registers of data page zero without the overhead of changing the DP or auxiliary register. Figure 3-3 illustrates memory-mapped addressing mode.

Figure 3-3. Memory-Mapped Addressing Mode

LAMM PMST

Internal Memory Organization

In the indirect addressing mode, the currently selected 16-bit auxiliary register AR(ARP} addresses the data memory through the auxiliary register file bus (AFB). While the selected auxiliary register provides the data memory address and the data is being manipulated by the CALU, the contents of the auxiliary register may be manipulated through the ARAU. See Figure 3-4 for an exam-ple of indirect auxiliary register addressing. Also, bit 7=1 defines this address-ing mode as indirect.

Figure ~. Indirect Addressing Mode

ADD *

Machine Code = 10

o

1 0 S H F T 11 10

o

⁰ 000 01

+

I

ARP

=

10 11+AR3

=

11 1

o

0 1 1 1 0 1 0

o

¹ 000 01 Operand Data(AR(ARP))

The operand may reside as part of the instruction machine code. In the case of the short immediate operand, the operand is contained in the single-word instruction. These short immediate operands vary in length from 1 bit on the SETC instruction to 13 bits on the MPY instruction. Figure 3-5 shows an ex-ample of short immediate mode. Note that, in this exex-ample, the lower eight bits are the operand and will be added to the ACC by the CALU.

Figure 3-5. Short Immediate Mode

ADD HOFFh

Machine Code

=

¹ .... 1_0_1_1 __ 1_0_0_0-=" ... 1_1 _1_1_1 _ _ 1_1--::1 ~1 1

---

---

----0-:'-1-: 1 1 1 1 1 -Operand

=

Operand = Data(ADD(7 - 0»

Internal Memory Organization

In the case of the long immediate operand, the operand immediately follows the opcode in the program sequence. The long immediate operand is 16 bits long. Figure 3-6 shows an example of long immediate mode. In this example, the second word of the two-word instruction is added to the ACC by the CALU.

Figure 3-6. Long Immediate Mode

ADD #01234h

Machine Code = t-1;...,;:0~---'-_--'-_1;...;~_~_0.=..-.0"'-'----"'S--'-H--'-F_T~

0 0 0 0 0 0 0 0 0 1 0 0

Operand = 0 0 0 1 001 0 001 1

o

^{1 0 0}

Operand = Data(second word(15 - 0))

The operand may come from a CPU register. This type of operand is used in special cases. The CALU uses this in multiplying with TREGO, in shifting with TREG1 and PM, and in bit manipulation with TREG2. The ARAU uses this with INDX and ARCR. The PLU uses this with DSMR. Figure 3-7 illustrates the use of the DSMR register as an AND mask in the APL instruction.

Figure 3-7. Register Access Mode

APL 010h

Machine Code =

I

0 1 0 1

o

1 0

01

0 0 1 0 0 0 01

7 7

/ /

/ /

1

I / /

~----~---~\ / /

\ / / / /

\/ /

~~~~~~~~~1~@~0~--~0~0-0~0~1

In the long immediate addressing mode, an operand is addressed by the sec-ond word of a two-word instruction. In this case, the program address/data bus (PAS) is used for the operand fetch. The PC is stored in a temporary register, and the long immediate value is loaded into the PC. Then, the PAS is used for the operand fetch or write. At the completion of the instruction, the PC is re-stored from the temporary register, and execution continues. This technique is used when two memory addresses are required for the execution of the

in-Internal Memory Organization

struction. The PC is used so that, when an instruction is repeated, the address generated can be autoincremented. Figure 3--8 illustrates this mode. In this illustration, the source address (OPERAND1) is fetched via PAB, and the des-tination address (OPERAND2) uses the direct addressing mode.

Figure 3-8. Long Immediate Addressing Mode

BLDD #02345h, 012h

Machine Code 1

=

¹¹

DP

=

₍₁ ¹

o

0 1 1

" " ^,

ORB

=

^{11 1}

o

0 Operand2

=

Data (ORB)

Machine Code2

. ^,," = .

¹⁰

PC

=

¹⁰

o

¹

Operand 1

=

^{Data (PC)}

o

1 0 1

1 0

11 _,

'\.

1 1 1 0

0 0 0

0 0 0 1

o

0 0 010 0 _; 0

o

_{1 0)}

I I

I I

I I

I I

I /

'\. I I

110 01

/

o

1

o

0 1

0 1 1 0 0 0 0 1 0 1 ;;»

I

"

0 0 0 0 0 1 1

,-Registered block memory addressing mode operates like the long immediate addressing mode with the exception that the address comes from BMAR. The advantage of this technique is that the address of the block of memory to be acted upon can be changed during execution of the program. The address in long immediate addressing mode resides in the program flow and cannot be easily changed. Figure 3-9 shows an example of registered block memory ad-dressing mode.

Internal Memory Organization

Figure 3-9. Registered Block Memory Addressing Mode

BLDD BMAR, 012h

Machine Code 1

=

11 0 1 0 1 1 0 0 010 0 1 0 0 01

DP

=

^{1 1 0 0} 1 1 1 0 11

\

,

\ \

ORB

=

^{11 1}

o

⁰ 1 1 1 0

i I

1 1

1 1

1 1

\ 1 1 /

\1 /

~~~~~~~~-1~Y~0~0~--0~0~1~0~1

Operand2

=

Data (ORB)

Dans le document TMS320C5x "TEXAS (Page 55-61)