Central Arithmetic Logic Unit (CALU)

The 'C5x central arithmetic logic unit (CALU) contains a 16-bit scaling shifter, a 16 X 16-bit parallel multiplier, a 32-bit arithmetic logic unit (ALU), a 32-bit accumulator (ACC), a 32-bit accumulator buffer (ACCB), and additional shift-ers at the outputs of both the accumulator and the multiplier. This section de-scribes the CALU components and their functions. Figure 3-12 is a block dia-gram showing the components of the CALU. The following steps occur in the implementation of a typical ALU instruction:

1) Data is fetched from memory on the data bus,

2) Data is passed through the scaling shifter and the ALU where the arithme-tic is performed, and

3) The result is moved into the accumulator.

One input to the ALU is always provided by the accumulator. The other input may be transferred from the product register (PREG) of the multiplier, the ac-cumulator buffer (ACCB) , or the scaling shifter that is loaded from data memory or the accumulator (ACC).

Central Arithmetic Logic Unit (CALU)

Figure 3-12. Central Arithmetic Logic Unit

ACCB(32)

3.5.1 Scaling Shifter

The 'C5x provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU; see Figure 3-12. The scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count is specified by a constant embedded in the instruction word or by the value in TREG 1. The LSBs of the output are filled with zeros; the MSBs may be either filled with zeros or sign-extended, depending upon the value of the SXM bit (Sign-extension mode) of status register ST1.

Central Arithmetic Logic Unit (CALU)

The 'C5x also contains several other shifters that allow it to perform numerical scaling, bit extraction, extended-precision arithmetic, and overflow preven-tion. These shifters are connected to the output of the product register and the accumulator.

3.5.2 ALU and Accumulator

The 'C5x 32-bit ALU and accumulator implement a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle.

Once an operation is performed in the ALU, the result is transferred to the ac-cumulator where additional operations, such as shifting, may occur. Data that is input to the ALU may be scaled by the scaling shifter.

The ALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In ad-dition to the usual arithmetic instructions, the ALU can perform Boolean opera-tions, faCilitating the bit manipulation ability required of a high-speed controller.

One input to the ALU is always supplied by the accumulator, and the other in-put may be furnished from the product register (PREG) of the multiplier, the accumulator buffer (ACCB), or the output of the scaling shifter (that has been read from data memory or from the ACC). After the ALU has performed the arithmetic or logical operation, the result is stored in the accumulator. For the following example, assume ACC = 0, PREG = 000222200h, PM = 00, and

The 32-bit accumulator (ACC) can be split into two 16-bit segments for storage in data memory; see Figure 3-12. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator re-main unchanged. When the postscaling shifter is used on the high word ofthe accumulator (bits 16 -- 31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0 - 15). When the postscaling shifter is used on the low word, the LSBs are zero-filled. For the following example, assume ACC = OFF234567h:

SACL TEMPI, 7 ;TEMPI

=

=

SACH TEMP2,7 ;TEMP2 = 91A2 ACC = OFF234567.

The 'C5x supports floating-point operations for applications requiring a large dynamic range. By performing left shifts, the NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator. The four bits of the TREG 1 define a variable shift through the scaling shifter for the ADDT/ LACT/SUBT instructions (add to / load to / subtract from accumulator

Central Arithmetic Logic Unit (CALU)

with shift specified by TREG 1). These instructions are useful in denormalizing a number (converting from floating-point to fixed-point). They are also useful in execution of an automatic gain control (AGC) going into a filter.

The single-cycle 1-bit to 16-bit right shift of the accumulator can efficiently align the accumulator's contents. This, coupled with the 32-bit temporary buffer on the accumulator, enhances the effectiveness of the CALU in extended-preci-sion arithmetic. The accumulator buffer register (ACCS) provides a temporary storage place for a fast save of the accumulator. The ACCS can also be used as an input to the ALU. The minimum or maximum value in a string of numbers can be found by comparing the contents of the ACCS with the contents of the ACC. The minimum or maximum value is placed in both registers, and, if the condition is met, the carry bit (C) is set to 1 . The minimum and maximum func-tions are executed by the CRLT and CRGT instrucfunc-tions, respectively. These operations are signed arithmetic operations. For the following examples, as-sume ACC=012345678h and ACCB= 076543210h:

CRLT ;ACC - ACCB - 12345678. C - 1.

CRGT ;ACC = ACCB

=

=

The accumulator's overflow saturation mode may be enabled/disabled by set-ting/resetting the OVM bit of STO. When the accumulator is in the overflow sat-uration mode and an overflow occurs, the overflow flag is set and the accumu-lator is loaded with either the most positive or the most negative value repre-sentable in the accumulator, depending upon the direction of the overflow. The value of the accumulator upon saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumula-tor without modification. Note that logical operations cannot result in overflow.

The 'C5x can execute a variety of branch instructions that depend on the status of the ALU and the accumulator. For example, execution of the instruction BCND can depend on a variety of conditions in the ALU and the accumulator.

The SACC instruction allows branching to an address stored in the accumula-tor. The bit test instructions (BITT and BIT) facilitate branching on the condition of a specified bit in data memory.

The 'C5x accumulator also has an associated carry bit that is set or reset, de-pending on various operations within the device. The carry bit allows more effi-cient computation of extended-precision products and additions or subtrac-tions. It is quite useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instruc-tions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. Examples of carry bit operations are shown in Figure 3-13.

Central Arithmetic Logic Unit (CALU)

Figure 3-13. Examples of Carry Bit Operations

C MSB LSB Shown in the examples of Figure 3-13, the value added to or subtracted from the accumulator may come from the input scaling shifter, ACCB, or PREG. The carry bit is set if the result of an addition or accumulation process generates a carry; it is reset to zero if the result of a subtraction generates a borrow.

Otherwise, it is cleared after an addition or set after a subtraction.

The ADDC (add to accumulator with carry) and SU BB (subtract from accumu-lator with borrow) instructions use the previous value of carry in their addition/

subtraction operation. The ADCB (add ACCB to accumulator with carry) and the SBBB (subtract ACCB from accumulator with borrow) also use the pre-vious value of carry.

The one exception to operation of a carry bit, as shown in Figure 3-13, is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator). This case of the ADD in-struction can set the carry bit only if a carry is generated, and this case of the SUB instruction can resetthe carry bit only if a borrow is generated; otherwise, neither instruction affects it. This feature is useful for extended precision arith-metic, as discussed in Chapter 7.

Two conditional operands, C and NC, are provided for branching, calling, re-turning, and conditionally executing according to the status of the carry bit.

The CLRC, LST #1, and SETC instructions can also be used to load the carry bit. The carry bit is set to one on a hardware reset.

The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions shift or rotate the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator's data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and

Central Arithmetic Logic Unit (CALU)

shifting in a zero. The repeat (RPT and RPTZ) instructions may be used with the shift and rotate instructions for multiple-bit shifts.

The SFLB, SFRB, RORB, and ROLB instructions can shift or rotate the 65-bit combination of the accumulator, ACCB, and carry bit as described above.

The accumulator can also be right-shifted 0 - 31 bits in two instruction cycles or 1 - 16 bits in one cycle. The bits shifted out are lost, and the bits shifted in are either zeros or copies of the original sign bit, depending on the value of the SXM status bit. A shift count of 1 to 16 is embedded in the instruction word of the BSAR instruction. For example, let ACC = 012345678h: