• 64K Byte and 256K Byte Versions
• On-Board Refresh Circuitry
• Byte Parity (odd) Generation and Detection
• Byte or Word Addressable
• Jumper Selectable Memory Map Assignment in Four Independent Blocks
• Read/Write Cycle Time 565 ns (max)
• LED Error Display
• Double Eurocard Form Factor
• VMEbus Compatible
• 0° C-70° C Operating Temperature Range
The MVME200 and MVME201 are VMEmodule Dynamic RAM boards used in VMEbus-based systems to increase global memory. Both mOdules provide four independent blocks of memory which can be located on appropriate boundaries throughout the 16 megabyte MC68000 address space. The modules use an 18-bit row organization to im-plement both byte and double byte (word) accessing and to implement byte parity generation and detection. Fig-ure 1 is a functional block diagram of the modules.
Both MVME200 and MVME201 are comprised of two 18-device rows of 200 ns dynamic RAM's. The 64K byte (32K words) MVME200 is organized into four 16K-byte blocks.
A capacity of 256K bytes (128K words) in 64K-byte blocks is provided by MVME201. The modules have refresh cir-cuitry and perform refresh every 16 MS. While refresh is in progress, any memory access is delayed until refresh completion. The modules have a header for jumper dis-abling of refresh generation, as a diagnostic aid.
MVME200 MVME201
Whether a write or read access is to the low or high or-der byte of a word is determined, respectively, by use of the VMEbus signals DSO* or DS1*, the lower and upper data strobes. Both data strobes are used to access a full word. Write and read cycle timing parameters are shown in Figures 2 and 3, respectively.
BASE ADDRESS SELECTION
The MVME200 and MVME201 modules each have four headers, one for jumper selection of a base address for each of the four blocks in which the total memory offered by the module is organized. The base address of any MVME200 block can be set on any 16K byte boundary.
The base address of any MVME201 block can be set on any 64K byte boundary. Address boundaries throughout the full 16 megabyte MC68000 address space can be chosen for both MVME200 and MVME201.
Unused blocks of memory must be jumper disabled.
An additional pin is provided for this in the base address selection header for each block on both modules.
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-96
o s:
FIGURE 1 - MVME200/201 Functional Block Diagram
A01-A15
I
MVME200, MVME201
WRITE CYCLE TIMING
The timing parameters for the cycle performed to write data in memory are shown in Figure 2. A write cycle is
initiated when WRITE*, followed by D80* and D81*, be-come active on the VMEbus.
FIGURE 2 - Write Cycle Timing Parameters
WRITE*
000-031
050'
051'
OTACK BERR
Parameter A B C D
II!I
2.0 V
Description Min Max
Valid data to D80* 0
DTACK* to invalid data 0
Cycle time 565 595
D80* to DTACK* 315 370
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-98
\\\\
Unit ns ns ns ns
MVME200, MVME201
READ CYCLE TIMING
The timing parameters for the cycle performed to read data from memory are shown in Figure 3. A read cycle is
initiated when WRITE* is inactive and DSO* and OS1* be-come active on the VMEbus.
FIGURE 3 - Read Cycle Timing Parameters
WRITE*
PI '\\\\\ Iff$
080* 2.0 V
.8
v
A
081*
E
000-031 3.2 V
1.5 V
OTACK
BERR _ _ _ _ ...J /
Parameter Description Min Max Unit
A Cycle time 565 595 ns
B Inactive DSO* to invalid data 10 ns
C Valid data to OTACK* 28 ns
D OSO* to active data 9 ns
E OSO* to OTACK* 330 385 ns
F Active data to inactive OTACK* 28 ns
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS
I
I
MVME200, MVME201
BYTE PARITY GENERATION CHECKING To insure the greatest integrity of stored data, MVME200 and MVME201 have circuitry for generating and checking byte parity (odd). On a write access, parity is calculated and the appropriate bit value is stored with the data byte.
On a read access, parity is re-calculated for the data byte and compared with the stored parity bit value.
When an error is detected, the local signal PAR ERR' is generated, causing an active open collector signal to be placed on the MVMEbus BERR* line. Simultaneously, the front panel PARITY ERROR light comes on. This red LED remains on until any byte is read without parity error.
As a diagnostic aid in determining a source of parity errors, both MVME200 and MVME201 have a header for disabling by jumper the generation of the VMEbus BERR*
signal on parity error detection. Disabling BERR* also disables the parity error indicator. An additional header equipped with four jumpers which allow parity to be forced in high and low memory bytes is only used for parity testing.
ALTERNATE ADDRESSING MODES
To provide a flexible means of using the VMEbus ad-dress modifier lines to implement system features such as separation of user access from privileged access in an operating system, MVME200 and MVME201 have a pro-grammable, bipolar, address modifier PROM (256 x 4).
The PROM decodes the states of the VMEbus IACK* and AMO through AM5 lines to produce four block select sig-nals which are applied to the mOdules' address decoder.
Response to a custom input code may be obtained by re-programming the address modifier PROM.
VMEbus INTERFACE
All VMEbus address and data signals and some control signals entering and leaving a module pass through buff-ers and/or latches. The LWORD* and all address lines are connected to active latches. Information on these lines is latched by a locally generated strobe. The IACK* and AMO through AM5 lines are connected to logic circuitry which generates a block select signal that is gated to the main address decoding circuitry by a locally generated strobe.
All data lines and the WRITE*, DSO* and DS1* signals are interfaced to buffered logic which generates local write, read, upper data strobe and lower data strobe signals and which transmits data when gated by a locally generated strobe. The VMEbus control signals BERR', DTACK* and SYSRESET* are interfaced directly to the module control circuitry.
MVME200/201 SPECIFICATIONS
The. specifications for MVME200 and MVME201 are listed in Table 1:
TABLE 1 - MVME200/201 Specifications
Characteristic Specification
Storage Capacity 64K Bytes (MVME200) 256K Bytes (MVME201) Word Length 8 Bits or 16 Bits
Memory Organization 16K Byte Blocks (MVME200) 64K Byte Blocks (MVME201) Write Cycle Time 595 ns max.
Read Cycle Time 595 ns max.
Error Detection Byte Parity, Odd
Input Loading One Schottky TTL Loaa Per Line
Output Loading Open-collector Output (lsink max. = 48 mAl Three-state Output (Isink max. = 64 mAl Temperature
Operating 0° to 70°C
StoraQe -550 to 850 C
Relative Humidity 0% to 90% (non-condensing) Power Requirements
MVME200 +5 Vdc @ 2.7 A (max.) +12 Vdc @ 0.5 A (max.)
MVME201 -12 Vdc @ 6.5 mA (max.)
+5 Vdc @ 3.3 A (max.)
Dimensions (Board Only) (With Front Panel)
Height 6.31 in. (160.3 mm) 7.40 in. (188 mm) Depth 9.19 in. (233.4 mm) 10.31 in. (261.9 mm) Thickness 0.062 in. (1.57 mm) 0.80 in. (20.32 mm)
MVME200/201 USAGE MVME110-1
VME/10 MVME101
VMEmodule Monoboard Microcomputer Microcomputer System
VMEmodule Monoboard Microcomputer
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-100
MVME200, MVME201
I
Ordering Information
Part Number Description
MVME200 VMEmodule 64K Byte Dynamic RAM with Byte Parity, Includes User's Manual
MVME201 VMEmodule 256K Byte Dynamic RAM with Byte Parity, Includes User's Manual
MVME200/D MVME200/201 64K/256K Byte Dynamic Memory Module User's Manual
Other VMEmodules Include:
Part Number Description
MVME101 VMEmodule Monoboard Microcomputer (8 MHz MC68000 MPU, Serial & Parallel Ports) MVME110-1 VMEmodule Monoboard Microcomputer
(8 MHz MC68000 MPU, Serial Port, 110 Channel)
MVME211 VMEmodule Static RAMIROM
(16 Sockets for up to 128K Bytes of RAM/ROM/PROM/EPROM) MVME300 VMEmodule GPIB Controller with DMA
(Provides IEEE-488 Listener, Talker, Controller Functions)
Related Documentation
VMEbus Specification Manual
I
L----~ HB212/0 _ _ _ __.~
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS