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I VMEmodule 1 Mb/2Mb Dynamic RAM ™ wNSB*

Dans le document VME Delta Series (Page 141-145)

• Supports VMEbusIVSB

• Dual-ported - 32-Bit Address/data VMEbus and Mul-tiplexed 32-Bit Address/data VSB Interface

• Interleaving - Two-way Interleaving on VMEbus or VS8

• Configurable Array - Dynamically Alterable to be Par-tially or Fully Private to the VSB Port. Selectable in 1/4 Population Increments

• Byte Parity Generation and Error Checking Circuitry

• Longword (32-bit), Word (16-bit). or Byte (8-bit) Data Transfers

• VMEbus Addressing - Automatic Selection of 24- or 32-Bit Addressing on VMEbus Interface, 32-Bit Ad-dressing on VSB

• Memory Base Address Settable on Board-Size Bound-aries throughout VMEbus and VSB Address Space

• Transparent Refresh Support

FUNCTIONAL DESCRIPTION

The MVME204-1 and MVME204-2 are VMEmodules offering, respectively, one and two megabytes of dual-ported dynamic RAM with parity for use with VMEbus and the dedicated, high-speed memory bus tailored for the MC68020 32-Bit Microprocessor - VSB. Interfaces to this bus enhance the performance of the MVME130 VMEmodule 32-bit Monoboard Microcomputer by al-lowing the transfer of data between the MVME130 and MVME204 modules concurrent with DMA transfers over VMEbus.

The one megabyte capacity of MVME204-1 is attained using 256K by 1-bit dynamic RAM devices. A mezzanine board containing an additional megabyte is added to achieve the two megabyte capacity of the MVME204-2.

Both modules have parity generation and detection cir-cuitry which, together with a VMEbus accessible control and status register, can be used for error detection and memory diagnostics.

Having a VMEbus interface, the modules can be applied in systems using this interconnect structure. Care must be taken with existing VMEmodule-based systems, since VSB and the extended 32-bit data and address use P2 of the VMEbus connector. The pins on connector P2 of the existing VMEbus system are commonly used as I/O pins.

VMEbus ADDRESS MODIFIER CODE RESPONSE VMEbus address modifier line decoding on the MVME204 provides response to both standard and

ex-*MVMX32bus is a Subset of the VME Subsystem Bus.

VMEmodule is a trademark of Motorola Inc.

MVME204-1 MVME204-2

Figure 1 is a functional block diagram of the modules.

tended, supervisory and non-privileged program and data accesses.

A programmable array logic device (PAL) is used for address modifier line decoding. This PAL is socketed to facilitate application of the modules in systems having speCial requirements.

VMEbus ADDRESS MAPPING

Both modules provide two switches (12 bits) used to select for a module, a base address in VMEbus address space. All 12 switch positions are used to set MVME204-1 VMEbus memory to begin on any MVME204-1024Kb boundary.

Eleven switch positions are used to set MVME204-2 VME-bus memory to begin on any 2048Kb boundary. The end-ing address in VMEbus space for a module is the sum of the starting address and the module population.

VSB Address Mapping

Both modules provide two switches (12 bits) used to select for a module a base address in VSB address space.

All 12 switch positions are used to set MVME204-1 mem-ory to begin on any 1024Kb boundary. Eleven switch po-sitions are used to set MVME204-2 memory to begin on any 2048Kb boundary. The ending address in VSB space for a module is the sum of the starting address and the module population. Note that an additional requirement is placed on the system programmer when the option of using non-identical starting addresses for a module in the VMEbus and VSB address spaces is chosen.

MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-106

MVME204-1, MVME204-2

STATUS/CONTROL REGISTER

An 8-bit, writable and readable Status/Control Register is used for controlling module functions and for reporting a parity error incurred during a VMEbus or VSB read ac-cess. The register is accessed by placing on the VMEbus address modifer lines the short supervisory I/O access code (hexadecimal 15}. Location in the VMEbus I/O space of the register is switch selectable.

The modules facilitate dynamic global/private memory allocation using three bits in the Status/Control Register.

Bit 6, when set, disables any VMEbus access in effect allocating all four module memory segments to access from VSB only. Various combinations of the states of bits 4 and 5 are used to remove one to four memory segments from VSB-only allocation and allow access also from VMEbus. Segment size is 256Kb and 512Kb for the MVME204-1 and MVME204-2, respectively.

Bit 3 of the Control/Status Register may be set to enable reporting via bus error of any VMEbus device attempting

256K RAM ARRAY

MULTIPLEXED

MVME204·1

~

ADDRESS

1 ROW OF 36 BITS '\[

MVME204·2 2 ROWS OF 36 BITS

32·BIT

/ t

ARRAY PARITY BITS

BUS 'C,/~

PARITY BUFFERS

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V r

~

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32·BIT DATA BUS

to access module memory allocated to private VSB access.

In applications where it is not desirable for the MVME130 system to cache the VSB port, this function may be disabled by setting bit 2 in the Control/Status Register.

For use in diagnostics, bit 1 in the Control/Status Reg-ister may be set to cause the wrong parity value to be written to an addressed location.

Two bits in the Control/Status Register are involved in parity control and reporting. The module indicates that a parity error has occurred on a VMEbus or VSB read access by setting bit 7 which is normally cleared from the VMEbus but can also be set for diagnostic use.

Bit 0 is set by the user to enable indication to a selecting device via the BERR* or MERR* signals of a parity error.

Module reporting of read access parity status via bit 7 is not affected by the state of bit

o.

ADDRESS

K

'J

DECODE AND MULTIPLEXING

/

'J

0

PARITY ERROR TIMING

DETECTION, AND

GENERATION CONTROL

.(~

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"-32·BIT ADDRESS BUS

,)

~

J

VSB INTERFACE

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VMEbus INTERFACE

VSB ~

\

VMEbus

n

Figure 1. MVME204 Functional Block Diagram

MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS

I

\

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MVME204-1, MVME204-2

MVME204 STATUS CONTROL REGISTER FORMAT

07 06 05 04 03 02 01 DO

PE RP PRl PRO PRBEREN MCACHE*

I

WWP EPER

PE: <Parity Error> The MVME204 status bit, when set indicates that a parity error has occurred from a VMEbus or VSB read access.

It can be cleared by writing a zero from the VMEbus or can be set for diagnostic purposes.

RP: <VSB Private> When set, RP disables any VMEbus access to the MVME204 DRAM array.

PR1,PRO: <Private RAM> PRl and PRO allocates the MVME204 DRAM array area to the VSB shown by the following table. These bits are "don't cares" when the RP bit is set.

PR1,PRO Memory Segment

VSB Accessible

00 3,2,1,0

01 3,2,1

1 0 3, 2

11 3

PRBEREN: <Private Bus Error Enable> When set, PRBEREN causes a Bus Error to be issued to the VMEbus device attempting to access

memory that has been allocated private to VSB by the PRl or PRO bits, or the RP bit of the MVME204 Control Register.

MCACHE*: <Memory Cacheable> When cleared allows the VSB port to be cached by the MVME130 system. MCACHE enables assertion of MCACHE* on the VSB with the same timing as MASACKO, 1 *. Indicating that the selected memory is cacheable.

WWP: <Write Wrong Parity> When set, causes the wrong parity to be written to the addressed location for diagnostic purposes.

EPER: <Enable Parity Error Report> When set, al-lows the MVME204 error detecting circuitry to report errors to the selecting device. Errors are indicated by the BERR* or MERR*. The PE bit in the MVME204 status/control register will not be affected by EPER. The PE bit will always indicate an error if one occurs. The EPER and WWP bits should not be set simultaneously.

'Active Low

MECHANICAL AND ENVIRONMENTAL SPECIFICATIONS

Characteristics Specifications

Power Requirements MVME204 - + 4.75 to 5.25 Vdc @ 5 A (max) Operating Temperature 0° to 55°C

Storage Temperature -40° to 85°C

Relative Humidity 5% to 95% (non-condensing) Physical Dimensions

Height 9.25 in. (23.50 cm)

Width 14.50 in. (36.83 cm)

Thickness 0.60 in. (1.52 cm) MVME204-1 0.75 in. (1.91 cm) MVME204-2

Storage Capacity 1Mb (MVME204-1)

2Mb (MVME204-2) Data Transfer Size 8-, 16-, 32-bits Error Detection Odd Byte Parity Data Input/Output 32-bit VMEbusNSB data

Input Address 32-bit VMEbusNSB addressing

MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-108

MVME204-1, MVME204-2

ORDERING INFORMATION

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Part Number Description

MVME204-1 VMEmodule 1024Kb Dynamic RAM with Byte Parity. Includes User's Manual.

MVME204-2 VMEmodule 2048Kb Dynamic RAM with Byte Parity. Includes User's Manual.

MVME204-1, -2/0 VMEmodule Dynamic RAM User's Manual.

RELATED PRODUCTS

Part Number Description

MVME130 VMEmodule 32-bit Monoboard Microcomputer with MC68020 CPU and VSB. Includes User's Manual.

MVME131 Same as MVME130 but also includes Memory Management Board.

MVME214 Static RAM/ROM VMEmodule with VSB. Includes User's Manual.

MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS

I VMEmodule 2Mb Dynamic RAM

Dans le document VME Delta Series (Page 141-145)