• Enhanced Performance Over the MVME204-2
• Supports VMEbusIVSB (VME Subsystem Bus)
• Dual-ported 32-Bit Address/Data VMEbus and Multi-plexed 32-Bit Address/Data VSB Interface
• Interleaving - Two-way Interleaving on VMEbus orVSB
• Cache and Non-Cache Operation
• Configurable Array - Dynamically Alterable to be Par-tially or Fully Private to the VSB Port. Selectable in 1/4 Population Increments
• Byte Parity Generation and Error Checking Circuitry
• Longword (32-bitj, Word (16-bit) or Byte (8-bit) Data Transfers
• VMEbus Addressing - Automatic Selection of 24- or 32-Bit Address on VMEbus Interface, 32-Bit Address-ing on VSB
• Memory Base Address Settable on Board-Size Bound-aries throughout VMEbus and VSB Address Space
• Transparent Refresh Support
FUNCTIONAL DESCRIPTION
The MVME204-2F is a VMEmodule offering two mega-bytes of dual-ported dynamic RAM with parity for use with VMEbus and the dedicated, high-speed secondary bus - VSB. Interfaces to VSB enhance the performance of processor modules such as the MVME130 by allowing the transfer of data between the MVME130 and the MVME204-2F modules concurrent with transfers over VMEbus.
The 2Mb capacity of the MVME204-2F is attained using 256K by l-bit dynamic RAM ZIP devices. The module has parity generation and detection circuitry which, together with a VMEbus accessible control and status register, can be used for error detection and memory diagnostics.
Having a VMEbus interface, the module can be applied in systems using this interconnect structure. Care must be taken with existing VMEmodule-based systems, since VSB and the extended 32-bit address and data use P2 of the VMEbus connector. The pins in rows A and C of P2 are commonly used on existing VMEmodules as I/O pins.
Figure 1 is a functional block diagram of the module.
VMEbus ADDRESS MODIFIER CODE RESPONSE The address modifier line decoding on the MVME204-2F provides response to both standard and extended, supervisory and non-privileged program and data accesses.
VMEmodule is a trademark of Motorola Inc.
MVME204-2F
A programmable array logic device (PAL) is used for address modifier line decoding. This PAL is socketed to facilitate application of the modules in systems having special requirements.
VMEbus ADDRESS MAPPING
The MVME204-2F provides two switches (11 bits) used to select a base address in VMEbus address space. These switches set the VMEbus base address to begin on any 2048Kb boundary. The ending address in VMEbus space is the sum of the starting address and the module pop-ulation (2Mb).
VSB ADDRESS MAPPING
The MVME204-2F provides two switches (11 bits) used to select a base address in VSB address space. These switches set the VSB base address to begin on any 2048Kb boundary. The ending address in VSB space is the sum of the starting address and the module popula-tion (2Mb). Note that an addipopula-tional burden is placed on the system programmer when tbe option of using non-identical starting addresses for a module in the VMEbus and VSB address spaces are chosen.
STATUS AND CONTROL REGISTER An 8-bit wide, writable and readable Status/Control Register is used for controlling module functions and for reporting a parity error incurred during a VMEbus or VSB read access. The register is accessed by placing on the VMEbus address modifier lines the short supervisory or short non-privileged I/O access code (hexadecimal 2D or 29). Location on word boundaries of the register in the VMEbus I/O space is switch selectable.
The module facilitates dynamic global/private memory allocation using bits 4, 5 and 6 in the Status/Control Reg-ister. Bit 6, when set, disables any VMEbus access, in effect allocating all four module memory segments to accesses from VSB only. Various combinations of the
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-110
MVME204-2F
states of bits 4 and 5 are used to remove one to four memory segments from VSB-only allocation and allow access also from VMEbus. Segment size is 512Kb.
Bit 3 of the Control/Status Register may be set to enable reporting via bus error of any VMEbus device attempting to access memory allocated to private VSB accesses.
In applications where it is not desirable for the mem-ory of the MVME204-2F to be cached through the VSB port, this function may be disabled by setting bit 2 in the Control/Status Register.
For use in diagnostics, bit 1 in the Control/Status
Reg-ister may be set to cause the wrong parity value to be written to an addressed location.
Two bits in the Control/Status Register are involved in parity control and reporting. The module indicates that a parity error has occurred on a VMEbus or VSB read access by setting bit 7, which is normally cleared from the VMEbus, but can also be set for diagnostic use. Bit
o
is set by the user to enable the indication to a selecting device via the BERR* or MERR* signals of a parity error.Module reporting of read access parity status via bit 7 is not affected by the state of bit
o.
MULTIPLEXED , . . . - - - .
,L-. ______ -,
ADDRESS ADDRESS
32-BIT ARRAY BUS
DECODE AND MULTIPLEXING
Figure 1. MVME204-2F Functional Block Diagram
MVME204-2F INTERLEAVING
To provide an increase in speed by decreasing access time, MVME204-2F VMEmodules support two way inter-leaving both on the VMEbus and on the VSB. Interinter-leaving is done by permitting a first module to handle even addresses and a second module to handle odd addresses so that the two appear as a single 4Mb module and are treated as such for data transfers. There is no limit to the number of pairs of modules that can be used in the inter-leave mode.
Interleaving provides the greatest speed increase for VMEbus write cycles because of the fast write mode built into the MVME204-2F VMEbus interface that allows the second module to be accessed while the first is com-pleting the access portion of its cycle.
VSB CACHE MODE OPERATION
In a system with a VMEbus processor having data cache capabilities, the MVME204-2F can operate in the cache mode. In this mode, significant access time is saved since the processor can begin a read access on the VSB before, as it normally would, determining a hit and receiv-ing the data from cache memory then terminatreceiv-ing the data transfer cycle. The MVME204-2F, in the cache mode, waits for the DS* signal (Data Strobe) before starting its internal memory read cycle to preclude being in this con-dition when the VSB cycle is terminated on a cache hit.
On a cache miss when the data is not in cache, the read cycle initiated by the processor continues to full completion.
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS
•
I
MVME204-2F
MVME204-2F Status/Control Register Format
07 06 05 04 03 02 01 00
PE VSBP PRl PRO
I
PRBERENI
MCACHE*I
WWP EPERPE: <Parity Error> The MVME204-2F status bit, when set, indicates that a parity error has occurred from a VMEbus or VSB read access.
It can be cleared by writing a zero from the VMEbus or can be set for diagnostic purposes.
PRBEREN: <Private Bus Error Enable> When set, PRBEREN causes a Bus Error to be issued to the VMEbus device attempting to access memory that has been allocated private to VSB by the PRl or PRO, and the VSBP bit of the MVME204-2F Control Register.
VSBP: <VSB Private> When set, VSBP disables any VMEbus access to the MVME204-2F DRAM array.
MCACHE*: <Memory Cacheable> When cleared, allows the VSB port to be cached. MCACHE* enables assertion of MCACHE* on VSB with the same timing as MASACKO,l*, indicating that the selected memory is cacheable.
PR1,PRO: <Private Ram> PR1 and PRO allocate the WWP: <Write Wrong Parity> When set, causes the wrong parity to be written to the addressed location for diagnostic purposes.
MVME204-2F DRAM array area to the VSB shown by the following table. These bits are
"don't cares" when the VSBP bit is set.
PR1, PRO
VSB Accessible 3,2,1,0
3,2,1 3,2
3
EPER:
Memory Segment
1
~--<Enable Parity Error Report> When set, allows the MVME204-2F error detecting cir-cuitry to report errors to the selecting device.
Errors are indicated by the BERR* or MERR*.
The PE bit in the MVME204-2F Control/Status Register is not affected by EPER and will always indicate an error if one occurs. The EPER and WWP bits should not be set simultaneously.
Access Sequence OS* to ACK* (VSB) AS* to ACK* (VSB) OS* to ACK* (VSB) AS* to ACK* (VSB)
*Active Low
MVME204-2F Timing (All times are typical values)
Write 135 ns (7) 235 ns (7) 135 ns (8) 235 ns (8)
Read 110 ns (7) 210 ns (7) 180 ns (7) 280 ns (7) AS* to OTACK* (VMEbus) 150 ns (8) 260 ns (10) AS* to OTACK* (VMEbus) 150 ns (8) 240 ns (9)
Notes 1,5 1,5 2,5 2,5 3,5 4,5 NOTES: 1. VSB is in the non·cacheable mode, which causes the MVME204-2F to start internal
DRAM access prior to receiving DS* from the initiating device.
2. VSB is in the cacheable mode, which causes the MVME204·2F to hold the actual DRAM access sequence until after DS* has been received from the initiating master.
3. VMEbus is not enabled for early release of DTACK*.
4. VMEbus is enabled for early release of DTACK*.
5. Numbers in parenthesis are the total number of cycles required to complete the specified transfer (read or write) when connected to the MVME130DON Processor Module, an MC68020·based monoboard microcomputer operating at 16.67 MHz.
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS 2-112
MVME204-2F
MECHANICAL AND ENVIRONMENTAL SPECIFICATIONS
Characteristics Specifications
Power Requirements + 4.75 to 5.25 Vdc (a 5 A (max)
Operating Temperature O°C to + 55°C inlet air temperature with forced air cooling
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O°C to + 40°C ambient, convection cooling Storage Temperature - 40°C to + 85°C
Relative Humidity 5% to 90% relative humidity (non-condensing) Physical Dimensions
Height· 9.25 in. (23.50 cm)
Width 14.50 in. (36.83 cm)
Thickness 0.60 in. (1.52 cm)
Storage Capacity 2Mb
Data Transfer Size 8-, 16-, or 32-bits
Error Detection Odd Byte Parity
Data Input/Output 32-bit VMEbusNSB Data
Input Address 32-bit VMEbusNSB Addres~
ORDERING INFORMATION
Part Number Description
MVME204-2F 2Mb, Dynamic RAM VMEmodule with odd byte parity and full 32-bit VMEbus and VSB interfaces. Includes User's Manual.
MVME204-2F/D MVME204-2F User's Manual.
RELATED PRODUCTS
Part Number Description
MVME130 VMEmodule 32-bit Monoboard Microcomputer with MC68020 MPU and VSB Interface. Includes User's Manual.
MVME131 VMEmodule 32-bit Monoboard Microcomputer with MC68020 MPU, Memory Management and VSB Interface. Includes User's Manual.
MVME130XT VMEmodule 32-bit Monoboard Microcomputer with MC68020 MPU, MC68881 FPCP, VSB Interface, a 16Kb Instruction/Data Cache and MVME130bug. Operates at 16.67 MHz. Includes User's Manual.
MVME131XT VMEmodule 32-bit Monoboard Microcomputer with MC68020 MPU, MC68881 FPCP, Memory Management, VSB Interface, a 16Kb Instruction/Data Cache and MVME130bug. Operates at 16.67 MHz.
Includes User's Manual.
MOTOROLA MICROCOMPUTER SYSTEMS AND COMPONENTS