Table 8-5 shows how floating-point accelerator macros are written for use with the as assembler. These macros should only be used if you have the HP 98248 floating-point accelerator.
To help you interpret the "as Syntax" column of the following table, here is a list of notations used:
YefpaS is the floating-point accelerator source.
YefpaD is the floating-point accelerator destination.
Yefpacr is the floating-point accelerator control register.
Yefpasr is the floating-point accelerator status register.
{ } indicates that the text between these braces is optional.
EA is the non-floating-point accelerator source.
L is a label.
SF is a floating-point size suffix that is required where shown:
Letter Means
s single precision
d double precision
SB is an MC68020/30/40 size suffix for a branch instruction that is optional. If this suffix is omitted and the -0 option for span-dependent optimization was not used, the default is . w.
However, if the -0 option is used span-dependent optimization selects the size.
Letter b w 1
Means
byte integer (8 bits) word integer (16 bits) long word integer (32 bits)
Instruction Sets 8-29
8
Table 8-5. FPA-Macro Formats
Mnemonic Assembler Syntax Operation
FPABS fpabs.SF %fpasS{,%fpaD} absolute value of operand FPADD fpadd.SF %fpasS ,%fpaD addition
FPAREG fpareg %an resets the address register to be used as the base register
FPBEQ fpbeq.SB L branch if equal
FPBF fpbf.SB L branch if false
FPBGE fpbge.SB L branch if greater than or equal FPBGL fpbgl.SB L branch if greater than or less than FPBGLE fpbgle.SB L branch if greater than, less than, or
equal
FPBGT fpbgt.SB L branch if greater than
FPBLE fpble.SB L branch if less than or equal
FPBLT fpblt.SB L branch if less than
FPBNE fpbne.SB L branch if not equal
FPBNGE fpbnge.SB L branch if not greater than or equal FPBNGL fpbngl.SB L branch if not greater than or less
than
FPBNGLE fpbngle.SB L branch if not greater than, less than, or equal
FPBNGT fpbngt.SB L branch if not greater than FPBNLE fpbnle.SB L branch if not less than or equal FPBNLT fpbnlt.SB L branch if not less than
8-30 Instruction Sets
Table 8-5. FPA-Macro Formats (continued)
Mnemonic Assembler Syntax Operation
FPBOGE fpboge.SB L branch if ordered greater than or equal
FPBOGL fpbogl.SB L branch if ordered greater than or less than
FPBOGT fpbogt.SB L branch if ordered greater than FPBOLE fpbole.SB L branch if ordered less than or equal FPBOLT fpbolt.SB L branch if ordered less than
FPBOR fpbor.SB L branch if ordered
FPBSEQ fpbseq.SB L branch if signalling equal FPBSF fpbsf.SB L branch if signalling false FPBSNE fpbsne.SB L branch if signalling not equal FPBST fpbst.SB L branch if signalling true
FPBT fpbt.SB L branch if true
FPBUEQ fpbueq.SB L branch if unordered or equal FPBUGE fpbuge.SB L branch if unordered or greater than
or equal
FPBUGT fpbugt.SB L branch if unordered or greater than FPBULE fpbule.SB L branch if unordered or less than or
equal
FPBULT fpbult.SB L branch if unordered or less than FPBUN fbpun.SB L branch if unordered 8
FPCMP fpcmp.SF Y.fpaS ,%fpaD compare
Instruction Sets 8-31
Table 8-5. FPA-Macro Formats (continued)
Mnemonic Assembler Syntax Operation
FPCVD fpcvd. 1 %fpaS { , %fpaD } converts long word integer to double precision
FPCVD fpcvd. s %fpaS { , %fpaD} converts single precision to double precision
FPCVL fpcvl. d %fpaS { , %fpaD} converts double precision to a long word integer
FPCVL fpcv1. s %fpaS { , %fpaD} converts single precision to a long word integer
FPCVS fpcvs . d %fpaS { , %fpaD} converts double precision to single precision
FPCVS fpcvs.1 %fpaS { , %fpaD } converts long word integer to single precision
FPDIV fpdi v . SF %fpaS , %fpaD division
FPINTRZ fpintrz.SF %fpaS { , %fpaD} rounds to integer using the round-to-zero mode
FPM2ADD fpm2add.SF EA, %fpaS ,%fpaD combination move to destination and addition
FPM2CMP fpm2cmp.SF EA,%fpaS ,%fpaD combination move to destination and compare
FPM2DIV fpm2di v. SF EA, %fpaS ,%fpaD combination move to destination and division
FPM2MUL fpm2mul.SF EA, %fpaS ,%fpaD combination move to destination and multiplication
FPM2RDIV fpm2rdi v .SF EA, %fpaS ,%fpaD combination move to
destinationand reverse division (i.e.
source + destination)
8-32 Instruction Sets
Table 8-5. FPA-Macro Formats (continued)
Mnemonic Assembler Syntax Operation
FPM2RSUB fpm2rsub.SF EA,%fpaS, %fpaD combination move to
destinationand reverse subtraction (i.e. source - destination)
FPM2SUB fpm2sub.SF EA,%fpaS ,%fpaD combination move to destination and subtraction
FPMABS fpmabs. SF EA, %fpaS { , %fpaD} combination move and taking absolute value of operand FPMADD fpmadd.SF EA,%fpaS ,%fpaD combination move and addition FPMCVD fpmcvd.1 EA, %fpaS { , %fpaD} combination move and convert long
word integer to double precision FPMCVD fpmcvd. s EA, %fpaS { , %fpaD} combination move and convert
single precision to double precision FPMCVL fpmcv1. d EA, %fpaS { , %fpaD} combination move and convert
double precision to long word integer
FPMCVL fpmcv1. s EA, %fpaS { , %fpaD} combination move and convert single precision to long word integer FPMCVS fpmcvs . d EA, %fpaS { , %fpaD} combination move and convert
double precision to single precision FPMCVS fpmcvs.1 EA, %fpaS { , %fpaD} combination move and convert long
word integer to single precision FPMDIV fpmdi v . SF EA, %fpaS { , %fpaD} combination move and division
FPMINTRZ fpmintrz.SF combination move and rounding 8
EA , %fpaS { , %fpaD} tointeger using round-to-zero mode FPMMOV fpmmov.SF EA, %fpaS , %fpaD combined move
Instruction Sets 8·33
Table 8-5. FPA-Macro Formats (continued)
Mnemonic Assembler Syntax Operation
FPMMUL fpmmul.SF EA, %fpaS, %fpaD combination move and multiplication
FPMNEG fpmneg.SF EA, %fpaS {, %fpaD} combination move and negation FPMOV fpmov.SF EA, %:fpaD move from an external location
fpmov.SF %fpaS, EA move to an external location
fpmov.SF %fpaS ,%fpaD move between two FP A registers fpmov. SF EA, %:fpasr move to the status register
fpmov.SF %fpasr, EA move from the status register
fpmov.SF EA, %:fpacr move to the control register
fpmov.SF %fpacr, EA move from the control register
8-34 Instruction Sets
Table 8·5. FPA·Macro Formats (continued)
Mnemonic Assembler Syntax Operation
FPMRDIV fpmrdiv.SF EA,%fpaS ,%fpaD combination move and reverse division(i.e. source -:- destination) FPMRSUB fpmrsub.SF EA, %fpaS , %fpaD combination move and
reversesubtraction (i.e. source -destination)
FPMSUB fpmsub.SF EA, %fpaS , %fpaD combination move and subtraction FPMTEST fpmtest.SF EA,%fpaS combination move and test of
operand FPMUL fpmul.SF %fpaS ,%fpaD multiplication
FPNEG fpneg.SF %fpaS{,%fpaD} negates the sign of an operand FPRDIV fprdi v .SF %fpaS , %fpaD reverse division (i.e. source
-:-destination)
FPRSUB fprsub.SF %fpaS ,%fpaD reverse subtraction(i.e. source -destination)
FPSUB fpsub.SF %fpaS , %fpaD subtraction
FPTEST fptest .SF %fpaS compares the operand with zero
FPWAIT fpwait generates a loop to wait for the
completion of a previously executed instruction
8
Instruction Sets 8·35