Overview of STMicroelectronics 28 nm CMOS FD-SOI Technology and Comparison

In this section, the technology used for circuit implementation is discussed briefly. It is the 28 nm CMOS FD-SOI node offered by STMicroelectronics. Interestingly, this technology benefits from an additional design flexibility at transistor level because of the introduction of a “back-gate” allowing a large body-biasing dynamic. Moreover, both reverse and forward body biasing are possible. Although this unique feature has not been used in this work, additional information may be found in multiple sources [Larie, 2015] [Cathelin, 2017].

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On top of solid front-end and back-end of line performances suitable for mmW operation, the choice of this technology is in fact mainly motivated by integration compatibility with high-speed and low-power digital circuits at relatively low costs. Meanwhile, 28 nm FD-SOI high frequency capability is studied in the following sections.

4.2.1. Front End of Line Performance

Figure 4-3: Superior FD-SOI transistor performance. Cross-section comparative view of a Bulk transistor (a) and a FD-SOI transistor (b) respectively. Transition frequency fT (c) and Maximum

Available Gain at 60 GHz (d) as measured in 28 nm FD-SOI (including full back-end of line parasitics). Data reproduced from [Shopov, 2014].

Figure 4-3 (a) and Figure 4-3 (b) present a cross-section comparative view of a FD-SOI transistor with respect to a traditional Bulk one. The introduction of a Buried Oxide layer enhances the electrostatic control of the channel and reduces source-drain parasitic capacitance. Consequently, peak transition frequency (fT) and peak maximum oscillation frequency (fmax) in excess of 300 GHz have been demonstrated in [Cathelin, 2017]. In Figure 4-3 (c), the fT is also investigated as a function of applied body biasing. It shows that optimum performance can be tuned to higher current densities, which is especially interesting in the design of high-frequency power amplifiers. Maximum Available Gain (MAG) is measured at 60 GHz in Figure 4-3 (d) in similar conditions. While peak MAG remain close to 10 dB, corresponding current densities also move to higher values, which is very desirable.

Such a very high frequency capability makes this technology node a very suitable choice for mmW circuit design.

Comparing these intrinsic performances to other technology nodes is very insightful. In Figure 4-4 (a) and Figure 4-4 (b), it is worth noting that RF CMOS technologies can compete with Silicon-Germanium Heterojunction Bipolar Transistors (SiGe HBT) and Indium-Phosphide (InP) HBT at the expense of more aggressive lithography processes. The use of SiGe HBT or InP HBT thus makes sense for RF purposes. However, the integration of high-speed

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digital functions at low cost (which is an important key success factor as mentioned earlier) is not satisfying. Besides, advanced CMOS technologies have the potential to meet all these needs. In this context, the 28 nm FD-SOI node clearly offers best-in-class performances among the CMOS devices thanks to a reduced gate length. In addition, pushing the reduction further seems attractive when considering the linear regressions in Figure 4-4, as even higher performances may be expected.

Figure 4-4: Summary of peak fT (a) and fmax (b) for different technological processes as a function of the critical lithography dimension (i.e., emitter width or channel length). Note that red squares represent the results of the DOTSEVEN project (SiGe HBT), while the brown crosses are the best InP HBT data

available. Figures reproduced from [Rinaldi, 2018].

Figure 4-5: FinFET high-frequency behavior investigation. (a) fT and fmax comparisons between the 28 nm (planar) and 14 nm (FinFET) technologies. (b) fmax and gate resistance evolution as a function of

the channel length in the 14 nm FinFET process. Figures reproduced from [Singh, 2018].

However, starting from the 22 nm node, the CMOS industry has actually moved from planar to 3D structures named FinFET. Mainly driven by improved digital performances and favorable area scaling, this topology unfortunately suffers from disappointing performances from the RF / mmW point of view, as illustrated in Figure 4-5 (a). In this figure, it is clear on both fT and fmax metrics that rather limited progress is actually offered to the RF designer.

Among other parasitics resulting from the FinFET architecture, Figure 4-5 (b) shows that detrimental gate resistances are responsible for significant fmax reduction, especially at lower channel lengths. Furthermore, the power dissipation capability, which is an important metric for most power amplifiers, is very constrained too because FinFET channels have a large

(a) (b)

(a) (b)

thermal isolation from the substrate. To sum up, the 28 nm CMOS FD-SOI node has been selected as an excellent traded-off for both digital and RF / mmW performances as well as fabrication costs.

4.2.2. Back End of Line Performance

Although FEOL performance is critical for the design of efficient mmW circuits, Back End of Line (BEOL) contribution is also significant. The ability to design high quality factors passive devices like transmission lines, inductors, transformers or baluns is in fact related to many technology parameters including the number of metal layers, their thicknesses, the total dielectric thickness and the substrate conductivity. In Figure 4-6, the most advanced standard processes from STMicroelectronics are compared qualitatively. Interestingly, the BEOL of the 28 nm FD-SOI node features two thick copper metal layers (≈ 1 µm) similar to those on CMOS 40 nm and 65 nm processes but singularly offers a thicker Aluminum Cap layer than previous nodes. Initially introduced to meet stringent mechanical rules (copper pillar assembly), this metal layer has also good RF characteristics because of low resistance and low parasitic capacitance. Besides, the comparison the BiCMOS 55 nm technology, which is fully dedicated to high-frequency applications, is instructive. Indeed, the presence of an additional very thick-copper layer (≈ 3 µm), far from the substrate, can also be leveraged for the design of low-loss mmW passive devices.

Figure 4-6: BEOL stacks comparison for advanced technology nodes available from STMicroelectronics (standard processes).

In order to provide insights on high-frequency capabilities of the previously evocated technologies, 50 Ω microstrip lines have been designed and simulated with Momentum. As an example, the simulation model used in 28 nm FD-SOI is shown in Figure 4-7 (a) while

CMOS 28 nm FD-SOI

BiCMOS 55 nm

CMOS 40 nm

CMOS 65 nm

attenuation results are summarized in Figure 4-7 (b). Due to its very high stack, BiCMOS 50 Ω microstrip is much larger, clearly exhibiting a superior performance. Nevertheless, advanced CMOS nodes show very acceptable results, especially as regards the CMOS FD-SOI one, with attenuations lower than 0.9 dB/mm. Although it is definitely not an exhaustive investigation, this school-case study highlights the mmW capability of the selected CMOS 28 nm FD-SOI.

Figure 4-7: Transmission lines simulations for different technology nodes. (a) simulation model and (b) simulated attenuations. Orange, red, green and blue refer to BiCMOS 55 nm, CMOS 28 nm

FD-SOI, CMOS 40 nm and CMOS 65 nm respectively.