ot AAD~ESS
B- ADDRESS REGISTER
Figure 4-6. Extraction of Indirect and Indexed Four-Character Addresses
TREATMENT OF ADDRESSES LARGER THAN A MEMORY'S MAXIMUM ADDRESS In all proce s sor s except a multicharacter proce s sor with maximum memory, it is pb s sible to specify in instructions direct addre s se s that are large r than the addre s s of the proc e s sor' s highe st memory location.
Likewise, it is possible in any Series 2000 processor, by the use of indexed addressing, to specify addre s se sand addre s s modifier s who se sums are potentially greater than the addre s s of the memory's highest location. For example, consider the case where, in a machine having a 49, 152-character memory, an instruction contains the address 49, 000 and the address is indexed using a register which contains the value 1, 000. Obviously, the sum of 49, 000 and 1, 000 is greater than the memory's highest address, 49, 151.
Situations such as the ones just cited are handled differently, depending upon the relation-ship between the potential address and the memory size involved and whether or not the Storage Protect feature is in effect. In particular, such situations can be categorized according to whether the potential address is larger or smaller than the range of addresses representable by active addre ss -register bits.
Potential Addresses Within Address Register Range
In a multicharacter processor without storage protection in effect, encountering a simple, direct address, or the potential sum of an indexed address and index register contents, which lies between the address of the highest actual memory location and the address registers' upper limit, causes the processor to stop. Results are unspecified for the other Series 2000 proces-sors. Any Series 2000 processor with Storage Protection in effect, upon encountering an address of the type described above, will perform the following actions: the internal interrupt
(II) address violation indicator is set, the instruction is terminated prematurely, and an internal interrupt is generated.
Potential Addresses Outside Address Register Range
In any Series 2000 processor, if a sim.ple direct address, or the potential sum. of an indexed address and index register contents, is greater than the largest address representable by active address-register bits, the resultant address is form.ed m.odulo the num.ber of locations addressable with the active address bits; i. e., a memory "wraparound" occurs. For ~xample,
in a 49K Model 2040, a total of 65, 536 locations can be add!essed by 16 active address bits. If, in such a machine, an address of 48, 000 is indexed by the value 27, 000, the resultant effective address will be 48, 000
+
27, 000 - 65,536, or 9464.EXPLICIT ADDRESSING, IMPLICIT ADDRESSING, AND CHAINING Consider the three instruction formats illustrated below.
OP CODE A ADDRESS B ADDRESS
FORMAT I. __ ~~~ __ ~~~~~ __ ~~~~ __
FORMAT 2. . .
---FORMAT 3. . .
Format 1 corresponds to the instructions used in the preceding illustrations. The signifi-cant feature of this format is that the addresses of both the A and the B data fields are explicitly
specified in the instruction. For this reason the data fields are said to be "explicitly addressed. Ii In general, whenever the programmer writes the address of a data field on his coding sheet, he is explicitly addreSSing that data field (see Figure 4-7).
EXPLICIT ADDRESS
1 1
OPCODE A ADDRESS 8 ADDRESS
•
-The addresses of both data fields are 'explicitly specified in the instruction.
Figure 4-7. Series 2000 Instruction Format I Format 2 has two pos sible interpretations (see Figure 4-8):
FORMAT I
1. Ten Series 2000 instructions coded in format 2 cause the A-address to be loaded into both AAR and BAR. 1 Thus, although the B-address portion of the instruction is omitted, the B-field is explicitly addressed by the A-address portion. The extraction path of these instructions is said to
"duplicate A" (see Appendix C), since the contents of AAR are duplicated in BAR.
2. The A-address of 19 instructions is loaded into AAR only, leaving BAR undisturbed. An omitted B addres.s in any of these instructions im.plies that the previous contents of BAR will be used as the addre ss of the B field. For this reason the B-field is said to be "impliCitly addre ssed, "
and the extraction path of these instructions "preserves B" (see Appendix C).
1 . .
The entire contents of AAR are loaded into BAR during extraction, so that all bit positions in BAR are identical to those in AAR. Recall that this is the only operation that affects bank bits and sector bits in two-character mode and sector bits in three-character mode.
EXPLIClr ADDRESS locations required to store the instructions.
IMPLlClr ADDRESS
As an example, assume that three 1 O-character fields stored in sequence are to be added to three other sequential fields. First, examine how this operation would be performed ~sing
explicit addressing. Upon completion of the first instruction, AAR contains 890 and BAR con-tains 690. These are the same values that appear in the A- and B-address portions of the second
o o
0)
900 890 880
700 690 680
instruction. Similarly, upon completion of the second instruction, AAR and BAR contain 880 and 680 - the A and B addresses of the third instruction. Since in each case AAR and BAR contain the addresses used in the next instruction, it is unnecessary to write these addresses in the in-struction. In other words, this operation could be performed using implicit addressing in the second and third instructions.
o 0) 0)
900 700
Connecting instructions together so that the contents of AAR, BAR, and the variant register (see below) at the conclusion of one instruction 'satisfy the requirements of the next instruction is called "chaining. II Using explicit addressing in the three-character addressing mode, 21 storage locations are required to store the instructions above and the operation takes 187 microseconds to complete on a Type 2041 processor. If the instructions were "chained,"
nine storage locations would be used and 168 microseconds would be required to complete the operation.
Instructions which require a variant character can also be chained by using the previous contents of the variant register. (The variant register is a single-character, internal register into which the variant character of an instruction is loaded during extraction.) The extent of chaining variant characters (i. e., the number of acceptable instruction formats in which the previous contents of the variant register can be used) varie s with the processor being used.
Variant characters can be chained by an instruction coded in any format (i. e., format 1, 2, or 3). The previous contents of the variant register are not normally distributed by the proces sing of an instruction which does not contain a variant character (see the instruction Branch, Move Characters and Edit, and Move and Translate for exceptions).
Chaining is not limited to sequential .operations having the same op code. The only con-dition that must be met is that an instruction must leave the contents of AAR, BAR, and, if required, the variant register such that they satisfy the addre s sing requirements of the next instruction in sequence.
To enable the programmer to chain instructions wherever possible, the description of each instruction (see Section VIII) include s a table showing the contents of the addre ss register s after the instruction has been executed. Also, Appendix C denotes whether each instruction in the machine complement can or cannot be chained.
SECTION V
EASYCODER PROGRAMMING
INTRODUCTION
The preparation of Series 2000 programs is greatly simplified by the use of Easycoder -a concise, e-asy-to-use progr-amming system. Specific-ally, E-asycoder relieves the progr-ammer of many time-consuming duties associated with writing a program in actual machine language.
It makes it unnecessary, for example, to maintain a careful record of the storage address as-signed to each instruction. In addition, it allows the programmer to employ meaningful sym-bolic tags (e.g., TAX, FICA, and TOTAL) rather than absolute memory addresses to specify data. In situations where a stored program must be relocated or modified, Easycoder can be used to perform the required alterations automatically.
Easycoder includes a number of assembly systems; these systems are:
• Easycoder A: Part of the Series 200/Basic Programming System.
Easycoder A operates in a system 'having a minimum main memory size of 4,0<;16 characters. (Additional memory, however, may be. used to adYantage.) . For additional information refer to Easycoder A Assembly System (Order No. BC28).
NOTE: A counterpart of Easycoder A - Easycoder A (P) - is available for use in a paper tape en-vironment. The main memory requirements are identical to those of Easycoder A. See Easycoder A (P) Assembly System (Order No.
BD42) for rnore information.
• Easycoder B: Also part of the Series 200/Basic Programming System • . Easycoder B operates in a system having a minimum main
memory size of 8, 192 characters. (Additional memory may be used to advantage, however.) See Easycoder B Assembly System (Order No. BA08) for additional in-formation.
• Easycoder C: Part of the Series 200/0perating System - Mod 1.
Easycoder C operates in a system having a minimum of 12,288 characters of main memory. (Additional memory, however, may be used to advantage.) For additional information refer to Easycoder Assemblers C and D (Order No. BA26).
• Easycoder D: Part of the Series 200/0perating System - Mod 1.
Easycoder D operates in a system having a minimum of 16,384 characters of main memory. (Additional memory however, may be used to advantage.) For additional infor-mation see Easycoder Assemblers C and D (Order No. BA26).
• as
/2000 Easycoder: Part of Series 200/2000 Operating System/2000.as
/2000 Easycoder operates in anas
/2000 partition having a minimum of 32K and a maximum of 256K memory.as
/2000 Easycoder implements operation codes with implied variants in addition to the standard instruction set. For additional information refer to OS/2000 Easycoder Assembler, (Order No. AH31).Each assembly system includes two basic elements: the Easycoder symbolic language and an Easycoder Assembler. The Easycoder language is used to write the symbolic program
(the source program) while the assembler is the programming element that translates the source program into the actual machine-language program (the object program).
To prepare a program in Easycoder symbolic language, the program.mer uses an Easy-coder Coding Form. (see Figure 5-5) and enters each symbolic instruction or definition on a
The assembler accepts the source-program cards and automatically produces a corre-sponding machine-language object program. It converts mnem.onic operation codes into ma";
chine language codes, assigns absolute storage addresses to instructions and symbolic operand references, and completely as sembles the final program, storing it on punched cards, disk units, or magnetic tape. Another output of the assembler may be a complete printed summary of the symbolic source program. and the corresponding machine -language entries. Figure 5-1 illustrates the relationship of the source program., assembler and object program.
SOURCE PROGRAM
Figure 5-1. Relationship of Source Program, Assembler, and Object Program
THE SYMBOLIC LANGUAGE
The Easycoder symbolic language is composed of a set of mnemonic. operation codes and a set of rules for defining memory areas, addressing operands, and entering constants. The mnemonic operation codes are predefiried abbreviations for machine-language operation codes and, in general, provide an easily remembered description of each instruction. For example, SI is the Easycoder mnemonic for the Set Item Mark instruction, and BCC is the mnemonic for the Branch on Character Condition instruction. The set of rules includes special mnemonics for defining work areas in the main memory and for defining programmer-specified constants.
The statements used in writing an Easycoder program can be classified into three groups:
1. Data formatting statements make it possible to reserve areas and store constants without regard to their actual locations in memory. Data for-matting statements are described in Section VI.
2. Assembly control statements are used by the programmer to control the assembly of his program. Assembly control statements are described in Section VII.
3. Data processing stateInents are the actual machine instructions to be exe-cuted in the object prograIn. Section VIII contains a description of the data processing statements eInployed by Series 2000 Central Processors.
THE ASSEMBLERS
The assembler element of each Easycoder assembly system translates the symbolic source prograIn (written on the Easycoder Coding Form and subsequently punched into a source-prograIn card deck) into Inachine-language entries, placing the resultant object pro-gram on either punched cards or magnetic tape. In addition to the object-propro-gram output, the assembler may also produce a printed listing containing the sYInbolic source program and the corresponding object-program entries (see Figures 5-2, 5-3, and 5-4).
OPERATION
Figure 5-2. Two-Character Address Assembly
SYMBOLIC
aulomalically
"'1
DIR'ECT INDEX;;:~~/::f* in II/i, ADDRESS REGISTER"
Figure 5-3. Three-Character Address Assembly
Figure 5-2 illustrates how an assembler assembles an object-program instruction using 2-character address assembly. Assume that the tag AMT is assigned to memory location 800 and that the tag TOTAL is assigned to memory location 1250. Figure 5-3 shows how the assem-bler assembles an object-program instruction using 3-character address assembly. Four-character addresses are assembled as shown in Figure 5-4. Assume that, in Figures 5-3 and
Figure 5-4. Four-Character Address Assembly
9
4 2