inter
SYSTEMS DATA CATALOG
JANUARY 1981
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7·104.9 (a) (9). Intel Cor- poration assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are implied.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
BXP Intelevision
CREDIT Intellec
i iSBC
ICE iSBX
ICS Library Manager
im MCS
Insite Megachassis
Intel Micromap
MULTIBUS' MULTI MODULE PROMPT Promware RMX UPI I'Scope and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS@ is a registered trademark of Mohawk Data Sciences Corporation.
~MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051
Quality Assurance Flow Chart CHAPTER 1
Single Board Computers
Table of Contents
iSBC 80104 Single Board Computer ... , . . . .. . . 1-1 iSBC 80105 or (pSBC 80105*) Single Board Computer. . . .. . . 1-7 iSBC 80/10B or(pSBC 80/10B*) Single Board Computer. . . .. . . . .. . . 1-12 iSBC 80/20-4 or(pSBC 80/20-4*) Single Board Computer. . . .. .. . . .. . . 1-19 iSBC 80/24 or(pSBC 80/24*) Single Board Computer. . . .. . . 1-26 iSBC 80/30 or (pSBC 80/30*) Single Board Computer. . . 1-35 iSBC 86/12A or(pSBC 86/12A *) Single Board Computer. . . 1-43 iSBC 88/40 Measurement and Control Computer ... , 1-51 iSBC 310 High Speed Mathematics Unit ... , . . . .. . . 1-59 CHAPTER 2
iSBXTM MULTIMODULETM Boards
iSBX331 Fixed Floating Point Math MULTIMODULE Board... 2-1 iSBX 332 Floating Point Math MULTIMODULE Board. . . 2-7 iSBX 350 Parallel 110 MULTIMODULE Board. . . .. . . .. . . .. . . 2-12 iSBX 351 Serial 110 MULTIMODULE Board. . . .. . . .. . . 2-16 CHAPTER 3
iCSTM Industrial Control Series "
iCS 80 Industrial Chassis ... " ...
~. . .3-1 iCS 910/920/930 Signal ConditioninglTermination Panels. . . . .. . . .. . . 3-6 iSBC941 Industrial Digital Processor _ ... '" . . . 3-14 CHAPTER 4
Run-Times Systems Software
iRMX/80 Real-Time Multi-Tasking Executive... ... 4-1 iSBC801 FORTRAN Run-Time Package... ... 4.6 iSBC 802 BASIC-80 Configurable RMX/80 Disk-Based Interpreter. . . .. . . .. . .
4~9iRMX860peratingSystem ... , ... , ... , .. ,... 4-13 iRMX88 Real-Time Multi-Tasking Executive... ... 4-25 iSBC 957 A Intellec-iSBC 86/12A Interface and Execution Package. . . 4-31 CHAPTER 5
Peripheral Controllers
iSBC 202 Double Density Diskette Controller. . . 5-1 iSBC 204 Single Density Flexible Diskette Controller. . . 5-4 iSBC 208 Flexible Disk Controller ... ,. . . 5-8 iSBC 215A/iSBC 21,5B Winchester Disk Controller. . . .. . . ... . . 5-12 iSBC 218 Flexible Disk Controller ...
~... ' 5-17 iSBC 220 SMD Disk Controller ... , . , . . . . .. .. . . 5-21 CHAPTER 6
Memory Expansion Boards
iSBC 01616K-Byte RAM Memory Board. . . 6-1 iSBC 032/048/064 RAM Memory Boards ... '" 6-3 iSBC 090 Memory System ... 6-5 iSBC 094 4K-Byte CMOS RAM Memory Battery Backup Board ... ,6-9 iSBC 2501 Megabit Bubble Memory Board ... 6-12 , iSBC 254 Bubble Memory Board ... ' ... :. . . 6-15 iSeC 41616K EPROM Expansion Board ... : .. . . 6-16 iSBC 464 or(pSBC 464*) 64K-Byte EPROM Expansion Board ... 6-18 iSBC 108A/116A Combination Memory and 1/0 Expansion Boards. . . 6-21 iSBC 300 or (pSBC 300*) 32K-Byte RAM Expansion Module iSBC 340 or (pSBC 340*)
16K-Byte EPROM Expanison Module ... :. . . 6-29
iSBC 301 4K-Byte RAM MULTIMODULE Board ...
~.. . . .. . .. . . 6-30
iSBC 337 MULTIMODULE Numeric Data Processor. . . 7·1 iSBC 501 Direct Memory Access Controller. . . .. 7·9 iSBC 508 I/O Expansion Board ... , . 7·13 iSBC 517 Combination I/O Expansion Board ... ; . . . 7·15 iSBC 519 or (pSBC 519*) Programmable I/O Expansion Board. . . .. . . .. . . 7·19 iSBC 530 Teletypewriter Adapter ... ; ... ; . . . 7·23 iSBC 556 Optically Isolated I/O Board ... '... . . .. . . 7·25 iSBC 569 Intelligent Digital Controller ... " . . . .. . . 7·27 CHAPTER 8
Communication Controllers
iSBC 534 or(pSBC 534*) FourChannel Communications Expansion Board... ... 8·1 ISBC 544 Intelligent Communications Controller. . . 8·5 CHAPTER 9
Analog I/O Expansion & Signal Conditioning Boards
iSBX 311 Analog Input MULTIMODULE Board ... ; . . . .. . . 9·1 iSBX 328 Analog Output MULTI MODULE Expansion Board ... ; . . . .. . . . 9·5 iSBX 711 Analog Input Board. . . . .. . . .. . . 9·9 iSBX 724 Analog Output Board ... ; . . . 9·13 iSBX 732 Analog Combination I/O Board ... 9·16 CHAPTER 10
System Packaging & Power Supplies
ISBC 604/614 or (pSBC 604/614 *) Modular Cardcage/Backplane . . . .. . . .. . . 10·1 iSBC 655 System Chassis ... ;... 10·3 iSBC 660 System Chassis ... 10·5 ISBC635 PowerSupply .. '... 10·8 iSBC640 PowerSupply ... 10·11 CHAPTER 11
Microcomputer Development Systems
Introduction' New Dimensions in Development Solutions ... , ... ,... 11·1 Model 120 Intellec Series II Microcomputer Development System ... '" : . . . 11·3 Model 225 Intellec Series 11/85 Microcomputer Development System ... 11·7 Model2861ntellec Series III Microcomputer Development System ... ,... 11-12 Model 290 Network Manager Intellec Network Development System·1 (NDS·1) . . . .. . . 11·18 CHAPTER 12
Microcomputer Development Systems Options
Expansion Chassis Intellec Series II Microcomputer Development System. . . • . . .. . .. . . . 12·1 Model 503 Double Density Upgrade Kit for Intellec Microcomputer Development System. . . 12·3 Model 505 Intergrated Processor Card ... '.' .... : . . . 12·5 Model 556 iAPX 86 Resident Processor Board Package. . . 12·8 Model 590 Network Manager Upgrade Package Intellec Network Development System·1
(NDS·1) .... · ... : .. 12·11 Model810 Software Development Module. . . .. 12·14 Mainframe Link for Distributed Development ... , ... , .. , ... ; ... ,... 12·18 Credit CRT·Based Text Editor Microcomputer Development Systems ... , ... , 12·21 CHAPTER 13
Flexible and Hard Disk Systems
Intellec Single/Double Density Flexible Disk System ...•... , . . . .. . . • . 13·1 Model 740 Intellec Hard Disk Subsystem. . . 13·5 CHAPTER 14
MCS 80185™ Development Systems and Options
FORTRAN 808080/8085 ANS FORTRAN 77lntellec Resident Compiler ... 14·1
Basic·80 Extended ANS 1978 Basic Intellec Resident Interpreter. . . 14·5
8080/8085 Fundamental Support Package (FSP) . . . 14-8 iCIS COBOL Software Package. . . .. 14-12 PUM 80 High Level Programming Language Intellec Resident Compiler. . . ..• 14-16 PASCAL 80 Software Package. . . 14-19 SP80 Support Package. . . .. 14-24 SP85 Support Package. . . .. 14-26 ICE-80, 8080 In-Circuit Emulator. . . .. 14-28 ICE-85B, MCS·85 In-Circuit Emulator with Multi-ICE Software. . . .. 14-34 CHAPTER 15
iAPX 86/88 Support Options
Series 118086/8088 Software Development Packages. . . 15-1 PUM 86/88 Software Package. . . .. 15-11 PASCAL 86/88 Software Package. . . .. . . .. 15-16 8087Software Support Package. . . .. 15-19 8089 lOP Software Support Package. . . .. . . .. . . . .. . . 15-22 SP86A/SP86B Support Package... .... ... ... ... 15-25 SP88 Support Package. . . .. 15-27 ICE-86, 8086 In-Circuit Emulator ... ,... 15-30 ICE-88, 8088 In-Circuit Emulator. . . 15-36 CHAPTER 16
Prototype Microcomputer Kits
SDK-85, MCS-85 System Design Kit. . . 16-1 SDK-86, MCS-86 System Design Kit .... , . . .. . . 16-7 SDK-C86, MCS-86 System Design Kit
Software and Cable Interface to Intellec Development System. . . 16-13 CHAPTER 17
MCS-48™ Development Systems
MCS-48 Diskette-Based Software Support Package. . . 17-1 ICE-49, MCS·48 In-Circuit Emulator. . . 17-3 HSE-49 High Speed Emulator. . . 17-7 EM1 8021 Emulation Board ... 17-13 EM2 8022 Emulation Board ... , . . . .. 17-16 ICE-22, 8022 In-Circuit Emulator. . . .. 17-19 CHAPTER 18
MCS-SPM Development Systems
8051 Software. Development Package. . . . .. . . 18-1 CHAPTER 19
UPI·41ATM Development Systems
ICE-41A, UPI-41A In-Circuit Emulator. . . 19-1 CHAPTER 20
2920 Signal Processor Development Systems
2920 Software Support Package. . . 20-1 CHAPTER 21
Memory Systems
Introduction ... , ... ;; .. . . 21-1 Series 90 General Purpose Memory System ... 21-2 in-5770 Video Refresh Memory System ... 21-5 in-1670, PDP*-11/70Add-On Memory System ... 21-11 in-5150 Eclipse Add-In Memory ... , .... , . . . .. . . .. 21-15 in-5160 Nova3 Add-In Memory ... ,.. . . .. .. . . .. . . .. . . .. . . .. . .... 21-19 MU-5780 VAX·11/780 Add-In Memory Card; . . . .. 21-24 CHAPTER 22
Insite
T "User's Program Library .... ; ... , ...• ' . .. . . .. .. . . .. . . .... ... . . . ... . .. . . . 22-1 CHAPTER 23
Intel Microcomputer Workshops ... 23-1 CHAPTER 24
Product Service 24-1
iii
A typical product flow
Visual Inspection of Printed Wire Assemblies
Automatic Test Systems Utilized in . Board Testing
Ovens Utilized for Board Pffj"Bake
Cable Testing Using an Automatic Test System
Checking Alignment of Floppy Disk Drives
ASSEMBLY
SYSTEM TEST
Aging in System Test
v
XYZ Measurement of Sheet Metal
In·Process QC of System in Assembly
Boot·Up Test in System Test
Shipping Inspection
Single Board
Computers 1
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iSBC 80/04
SINGLE BOARD COMPUTER
• 8085A CPU used as central processor
• 256 bytes of static readlwrite memory
• Sockets for 4K bytes of erasable reprogrammable read only memory
• 22 programmable parallel 1/0 lines with sockets for interchangeable line drivers and terminators
• Optimized for stand-alone applications with provisions for on-board + 5V regulator, heat sink, and mounting holes for attachment to user's equipment
• Programmable 14-bit binary timer
• TTL serial 110 interface with hole patterns for RS232C line drivers and receivers
• Four-level vectored interrupt
• Upward compatibility with iSBC 80/05
• Single + 5V power supply
The iSBC 80/04 Single Board Computer is a member of Intel's complete line of OEM computer systems which take full advantage of Intel's LSI technology to provide economical, self·contained computer·based solutions for OEM applica·
tions. The iSBC 80/04 is a complete computer system on a single 6.75 x 7.85·inch printed circuit card. The CPU, system clock, readlwrite memory, nonvolatile read only memory, 1/0 ports and drivers, serial interface, priority interrupt logic, and programmable timer all reside on the board.
1·1
FUNCTIONAL DESCRIPTION
Intel's powerful8-bit n-channel8085A CPU, fabricated on a single LSI chip, is the central processor for the iSBC 80104. The 8085A CPU is directly software compatible with the popular intel8080A CPU. The 8085A contains six 8-bit general purpose registers and an accumulator. The six general pwpose registers may be addressed individ- ually or in pairs, providing both single and double preci- sion operators. Minimum on-board instruction execu- tion time is 2.03 microseconds. A block diagram of iSBC 80104 functionalcomponents is shown in Figure 1.
Memory Addressing
The 8085A CPU has a 16-bit program counter which allows addressing of up to 65,536 bytes of memory. An external stack, located within any portion of iSBC 80104 readlwrite memory, may be used as a last-inlfirst-out storage area for the contents of the program counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls the addressing of this external stack. This stack provides subroutine nesting bounded only by memory size.
Memory Capacity
The iSBC 80104 contains 256 bytes of readlwrite memory using the Intel 8155 RAMIIOITimer. Two sockets for up to 4'K bytes of nonvolatile read only memory are pro- vided on the board. Read only memory may be added in 2K-byte increments using Intel 2716 erasable and elec- trically reprogrammable ROMs (EPROMs) or Intel 2316E masked ROMs. Optionally, if only 2K bytes are required, read only memory may be added in 1 K-byte increments using Iniel 2708 EPROMs or Intel 2608 masked ROMs.
Parallel 1/0 Interface
The iSBC 80104 contains 22 programmable parallel ,1/0 lines implemented using the 110 ports of the Intel 8155
22 PROGRAMMABLE I/O LINES
RAMIIOITimer. The system software is used to con- figure the 110 lines in any combination of unidirectional input or output ports as indicated in Table 1. The 110 in- terface may, therefore, be customized to meet specific peripheral requirements. In order to take full advantage of the large number of possible 110 configurations, sockets are provided for interchangeable 110 line drivers and terminators. Hence, the flexibility of thelIa inter- face is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polar- ity, and driveltermination characteristics for each appli- cation. The 22 programmable 110 lines and signal ground lines are brought out to a 50-pin edge connector that mates with flat, woven, or round cable.
Stand·Alone Applications
The iSBC 80104 is designed to be a cost-effective solu- tion for applications requiring a self-contained com- puter on a single board without the need for external memory or 110 options. In order to help minimize power supply cost in small systems, the iSBC 80104 includes provision for an on-board
+
5V regulator allowing unreg- ulated voltage to be connected directly on the board.Regulated DC voltages are applied to the board through two 12-pin edge connectors which mate with flat, woven, or round cables. The iSBC 80104 also includes pins that will accept MOLEX-type connectors for con- nection of regulated DC voltages. Mounting holes are provided in the corners of the iSBC 80104 board which permit direct attachment to the user's equipment, thereby eliminating the need for cardcage and back- plane.
Compatibility with iSBC 80105
TheiSBC 80104 is fully upward compatible with the iSBC 80105 Single Board Computer. Pin assignments for parallel 110, serial 110, and regulated DC voltages are
EXTERNAL INTERRUPT REQUEST LINE
SERIAL I/O INTERFACE
ITTLlEVELS)
SERIAL I/O INTERFACE IRS2J2C LEVELSI
Figure 1. ISBC Block Diagram Showing Functional Components
iSBC 80/04
Table 1. Input/Output Port Modes of Operation Mode of Operation
Unidirectional
Port Lines Input Output Control
(qty)
Latched & Latched &
Unlatched
Strobed Latched
Strobed
1 8 X X X X
2 8 X X X X
3 3 X X X1
4 3 X X X2
Noles
1. Port 3 must be used as a control port when port 1 is used as a latched and strobed input or a latched and strobed output port.
2. Port 4 must be used as a control port when port 2 is used as a latched and strobed input or a latched and strobed output port.
indentical to those of the iSBC 80/05. Additionally, soft·
ware developed for the iSBC 80/04 will execute directly in the iSBC 80/05. In addition to the iSBC 80/04 features, the iSBC 80/05 contains a total of 512 bytes of read/write memory, allows for expansion of memory and I/O capacity, and provides full MULTI BUS arbitration con·
trol for multimaster applications.
Programmable Timer
The iSBC 80/04 provides a fully programmable binary 14·bit interval timer utilizing the Intel 8155 RAM/la/Timer. The systems deSigner simply configures the time via software to meet system requirements.
Whenever a given timer delay is needed, software com·
mands to the programmable timer select the desired functions. Four functions are available as shown in Table 2. The contents of the timer counter may be read at any time during system operation.
Table 2. Programmable Timer Functions Function
Programmable pulse
Square wave rate generator
Rate generator
Programmable strobe
Operation
Timer out goes low during the sec·
ond half of count. Therefore, the count loaded in the count length register should be twice the pulse width desired.
Timer out remains high until one·
half the count has been completed, and goes low for the other half of the count. The count length is auto·
matically reloaded when terminal count is reached.
Divide by N counter. A repetitive timer out low pulse is generated and new timeout initiated every time ter·
minal count is reached.
A single low pulse is generated upon reaching terminal count. This func·
tion is extremely useful for genera·
tion of real·time clocks.
1·3
Serial I/O Interface
The iSBC 80/04 prvides serial I/O capability through the serial input data (SID) and serial output data (SOD) func·
tions of the Intel 8085A CPU. These functions are con·
trolled exclusively by software through execution of the 8085A RIM and SIM instructions. The baud rate for the serial I/O interface is determined by the system time available for execution of serial I/O support software.
Hence, the maximum baud rate supported by the iSBC 80/04 is solely dependent on the overall system real·
time software requirements. Serial I/O signals are TTL compatible, and hole patterns are provided on the board for optional installation of RS232C line drivers and receivers.
Interrupt Capability
The iSBC 80/04 takes advantage of the powerful inter- rupt processing capability of the 8085A CPU. Interrupt requests are routed to four interrupt inputs of the 8085A CPU (i.e., TRAP, RST 7.5, RST 6.5, and RST 5.5 in order of priority, TRAP highest), and each input generates a unique memory address (i.e., TRAP: 2616, RST 7.5: 3C16, RST 6.5: 3416, RST 5.5: 2C16 ). A single 8085A jump in- struction at each of these addresses then provides linkage to locate each interrupt service routine in- dependently anywhere in memory. All interrupt inputs with the exception of one (TRAP) may be masked via software. The trap interrupt should be used for condi- tions such as power-down sequences which require at- tention by the 8085A CPU.
Interrupt Generation - The iSBC 80/04 accepts inter·
rupts from four sources. An interrupt is automatically generated by the programmable interval timer/event counter upon completion of the selected function. Two interrupts are automatically generated by the I/O ports section of the 8155 when ports 1 or 2 of the 8155 are pro- grammed to operate in the "latched and strobed" mode (see Table 1). The fourth interrupt source is available to the user and should be used to inform the 8085A CPU of catastrophic errors such as power failure. This user- defined source is connected to the trap input of the 8085A CPU.
Systems Development Capability
The development cycle of the iSBC SOl04-based prod- ucts may be significantly reduced using an Intellec microcomputer development system. The resideni macroassembler, text editor, and system monitor greatly simplify the design, development, and debug of iSBC SOlO4 system software: An optional diskette oper- atingsystem provides a relocating macroassembler, a relocating loader and linkage editor, and a library mana- ger. A unique in-circuit emulator (ICE-S5) option pro- vides the capability of developing and debugging soft- ware directly on the iSBC S0104.
Programming Capability
PL/M-80 - Intel's high level programming language, PUM, is also available as a resident Intellec microcom- puter development system option. PUM provides the
SPECI FICATIONS Word Size
Instruction - S, 16, or 24 bits Data - S bits
Cycle Time
Basic Instruction Cycle - 2.03 I'S, ± 0.1 % Note
Basic instruction cycle is defined, as the fastest instruction (i.e., four clock cycles).
Memory Addressing
ROMIEPROM - O-OFFFH RAM - 3FOO H
Memory Capacity
ROMIEPROM - 4K bytes (sockets only) RAM - 256 bytes
1/0 Addressing
On-Board Programming 1/0 - see Table 1
Port 8155 8155 8155 8155 8155 Timer Control Port 1 Port 2 3&4 .Ports Low·Order
Byte
Address 00 01 02 03 04
1/0 . Capacity
8155 Timer Hlgh·Order
Byte 05
Parallel - 22 programmable lines (see Table 1)
Serial Communications Characteristics
SID and SOD functions of the S085 CPU are used for serial 1/0. Controlled by software through RIM and SIM instructions of the SOS5A CPU. Baud rate determined by system time available for serial 1/0 handling, On-board timer may be used to greatly ease serial 1/0 timing re- quirements.
capability to program in a natural, algorithmic language and eliminates the need to manage register usage or allocate memory. PUM programs can be written in a much shorter time than assembly language programs for a given application.
FORTRAN-BO - For applications requiring computa- tional and formatted 1/0 capabilities, the high level FORTRAN-SO programming language is also available as a resident option of the Intellec system. The FOR- TRAN compiler produces relocatable object code that may be easily linked with PUM or assembly language program modules. This gives the user a wide flexibility in developing software.
Interrupts
Four-level interrupt routed to SOS5 CPU interrupt inputs.
Each interrupt automatically vectors the processor to a unique memory location
Condition Interrupt Memory
Priority Type Input Address
User·defined TRAP 2416 Highest Non-rnaskable
Timer RST 7.5 3C16
t
Maskable1/0 Port 2 RST 6.5 3416 Maskable
1/0 Port 1 RST 5.5 2C16 Lowest Maskable
.,
Timer
Input Frequency Reference - 122.SS ·kHz ± 0.1 % (S.14 I's period nominal)
Output FrequencieslTimlng Intervals
Function TlmerlCounter
Min Max
Programmable pulse 8.14 ~s 66.67ms
Square' wave rate generator 7,50 Hz 61.44 kHz
Rate generator 7.50 Hz 61.44 kHz
Programmable strobe 8.14 ~s 133.33 ms
Interfaces
Parallel 1/0 - All signals TTL compatible
Interrupt Request - All TTL compatible (active-low) Serial 1/0 - TTL; hole patterns available for user instal- lation of RS232C line drivers and receivers
System Clock (8085 CPU)
1.966 MHz ±0.1%
iSBC 80/04
ConnectorsPins Center
Interface (no.) (In.) Mating Connectors 1
Molex 09·66·1071 Connector Molex 09·50·7071
7 Connector
+ 5V, + 12V,
single· 0.156 _ 5V 2
sided
AMP 87194·6 Connector AMP 3·87025·4
Connector
Molex 09·66·1071 Connector Molex 09·50·7071
7 Connector
Voltages + 5V, -12V3 single- 0.156 sided
AMP 87194·6 Connector AMP 3·87025·4
Connector
Molex 09·66·1021 Connector Molex 09·50·7021
2 Connector
Unregulated
single- 0.156
+5V sided
AMP 89194·1 Connect"or AM P 2·87025·5
Connector
50 3M 3415·000
Parallel 1/0 double· 0.1
(flat cable) sided
MOlex 09·66·1071 Connector Molex 09·50·7071
7 Connector
Serial 1/0 single· 0.156 ended
AMP 87194·6 Connector AMP 3·87025·4
Connector
Notes
1. Connectors and pins from a given vendor may only be used with can·
nectars and pins from the same vendor.
2. A single 86~contact edge·on connector may be used to connect the two groups of regulated voltages (I.e., + 5V, + 12V, - 5V, and + 5V, -12V).
3. Required only when RS232C line drivers and receivers are used.
1-5
Line Drivers and Terminators
110 Drivers - The following line drivers are all compati·
ble with the I/O driver sockets on the iSBC 80/04:
Driver Characteristic Sink Current (rnA)
7438 I,OC 48
7437 I 48
7432 NI 16
7426 I,OC 16
7409 NI,OC 16
7408 NI 16
7403 I,OC 16
7400 I 16
Note
I;;; inverting; NI;;; non-inverting; OC;;;;: open collector.
I/O Terminators - Intel provides 220Q/330Q divider and 1 kQ pull·up resistive terminator packs for termination of 110 lines programmed as inputs. These options are as follows:
220Q
+5V - - - ; : - - - ,
220QI330QL ~---+----~O isec 901 OPTION
1 kQ
1 kQ + 5V ----~'VV\_---__o isec 902 OPTION
RS232C Drivers and Receivers
The following RS232C drivers and receivers are compati·
ble with the RS232C socket on the iSBC 80/04:
RS232C Driver - National DS1488 or TI SN75188 RS232C Receiver - National DS1490 or TI SN75189
Sockets
Sockets may be installed in the hole patterns provided ior the RS232C drivers and receivers. The following sockets are compatible with the iSBC 80/04: TI C93·14·02 and SCANBE US·2·14·160·N·B.
Compatible Voltage Regulator National LM 323 - 3A, 5V Positive Regulator Fairchild J.<A7805 KM - 1 A, 5V Positive Regulator
Compatible Heat Sink IERC - LA Series or
AAVID Engineering, Inc. - Series 5051
Physical Characteristics Width - 7.85 in. (19.94 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 6.0 OZ (169.9 gm)
~---_-~--7."'---_
.lD9DIA
I ~ ~.I25REF
6 . 7 6 7 - - - -
- 0 -I
,,146 I
Sl' I
'.20 '.75IJ"""
- - - 7 . 8 5 ----~Figure 2. ISSC 80/04 Dimensions
Electrical Characteristics
DC Power Requirements
Voltage Without
(:1:5"10) PROM1 (max)
Vee= +5V lee= 600 mA
VOO= + 12V4 100=0
VBB= -5V 4 IBB=O
VAA= -12V 5 IAA=O
Note.
With 2716 With 2708 EPROM2 EPROM3
(max) (max) 1.45A 1.25A
7 mA5 137mA
0 90 mA
23 mA5 23 mA5
1. Ooes not Include power required for opiional EPROMIROM, 110
drivers, and 110 terminators. .
2. With' two Intel 2716 EPROMs and 220111330!'l terminators Inslalled for 22 input ports; all terminator inputs low.
3. With two Intel 2708 EPROMs and 22011133012 terminators installed for 22 Input ports; all terminator inputs low.
4. Required for 2708 EPROMs.
5. Required only when RS232e capability required.
ORDERING INFORMATION Part Number
SBC 80/04
Description
Single Board Computer
Environmental Characteristics
Operating Temperature - O·C to
+
55·CReference Manual
9800482·02 -iSSC 80/04 Hardware Reference Manual (NOT SUPPLIED)
Reference manuals are shipped with each product only if designated SUPPLIED (see above). Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
iSBC 80/05 or (pSBC 80/05*) SINGLE BOARD COMPUTER
• 8085A CPU used as central processor
• 512 bytes of static read/write memory
• Sockets for 4K bytes of erasable reprogram mabie or masked read only memory
• 22 programmable parallel I/O lines with sockets for interchangeable line drivers and terminators
• Full MULTIBUS control logic allowing up to 16 masters to share system bus
• Programmable 14-bit binary timer
• TTL serial I/O interface with sockets for RS232C line drivers and receivers
• Four-level vectored interrupt
• Fully compatible with optional iSBC expansion boards and peripherals
• Single + 5V power supply
The iSSC 80105 Single Soard Computer is a member of Intel's complete line of OEM computer systems which take full advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for OEM applica- tions. The iSSC 80105 is a complete computer system on a single 6.75
x
12.00-inch printed circuit card. The CPU, system clock, readlwrite memory, nonvolatile read only memory, 110 ports and drivers, serial interface, priority inter- rupt logic, programmable timer, MULTI SUS control logic, and bus expansion buffers all reside on the board.'Same product, manufactured by Intel Puerto Rico, Inc.
1-7
FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel 8085 CPU, fabricated on a single LSI chip, is the central processor for the, is,Be 80/05. The 8085A CPU is directlysoftVo(are compatible with the popular Intel8080A CPU.The 8085Acontains six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed indivi~
ually or in pairs, providing both single and double preCi- sion operators. Minimumoh-board instruction execu- tion time is 2.03 microseconds. A block diagram of iSBC 80/05 functional componentsis shown in Figure 1.
Memory Addressing
The 8085A CPU has a 16-bit program counter which allows direct addressing of up to 65,53S'bytes of mem- ory. An external stack, located within any portion of readlwrite memory, may be uS,edas a last-inlfirst-out storage area fo~ the coritents"of the program counter, flags, accumulator, and all of ,tl)e "six generalpurp~se
registers. A 16-bit stack pointer controls the addressing of this external stack. This stack provides subroutine nesting bounded only by memory size." '""
figure the 1/0 lines in any combination of unidirectio~al input or output ports as indicated in Table 1. The I/O In-
, Jerfacemay, therefore, be customized to meet specific peripheral requirements. In order to take full advantage of the large 'number· of possible I/O configurations, 'sockets are provided for interchangeable I/O line drivers and terminators. Hence the flexibility of the 1/0 interface is further enhanced by the capability of selecting the ap- propriate cpmbination ,of optional line 'drivers and, ~er
minators to provide the required sink current, polanty, and drivellertnination characteristics for each applica- tion. The 22 programmable I/O lines and signal ,ground lines are"b"rought out to a40-pin'edge connector that mates with flat, Woven, or round cable. "
Multimaster Capability
TheiSSC 8085Ais ~ full computer on a Single board wiih reso'urces capable of supporting a great variety of OEM system requirements. For those applications requiring additional, processing capacity and the benefits of multiprocessirig(i.e., several'CPUs andlol'controllers logically share'systems tasks with communicatioriover the system bus), the iSBC (l0/05 provides full MULTIBUS arbitra,tion control logic. This control logic"allows up to Memory Capacity
,
tlireebus
masters (i.e., any combination cifiSBG80/05, TheiSBC 80/05 contains 512 bytesofread/write memory' [SBe80/20~4;
OrillA c;ontroller;diske,tte controller,etc.) to using !ntel's IQw power static RAMs.,Two sockets forup 'share the system bus' in serial, (dai!ly-chain), priority to 4K bytes of nonvolatile, re,ad only memory are pro, fashlon,arid up to 16 masters mayshare tlie'MULTIBUS vided on the board. Read only memory, may be added in with the addition of an external priority network. The 2K-byte increments using Intel 2716 erasable and elec- MULTIBUS arbitration logic operates synchronously trically reprogram mabie ROMs (EPROMs) or Intel 2316E with a MULTI BUS clock (provided by the iSBC 80/05 or masked ROMs. Optionally, if only 2K bytes are required, optionally connected directiy to the MULTIBUSclock) read only memory may be added in 1K-byte increments while data is transferred via a handshake between the using Intel 2708 EPROMs or Intel 2608 masked ROMs. master and slave modules. This allows different speed controllers to share resources on the same bus, and for Parallel 110 Interface transfers via the bus to proceed asynchronously. Thus, The iSBC 80/05 contains 22 programmable paralfel 1/0 transfer,speed is dependent on transmitting and receiv- lines Implemented using the 1/0 ports of the Intel, 81,55 ing devices only. This design prevents ~Iow master RAM/IOlTimer., The system softwarei~ used to"con,,<,';,modules from being,handicapped in, their attempts toFigure 1_, iSBC 80105 Block Diagram Showing Functional Components
iSBC 80/05
Table 1. Input/Output Modes of Operation Mode of Operation
Unidirectional
Port Lines
Input Output Control
(qty)
Unlatched Latched&
Latched Latched &
Strobed Strobed
1 8 X X X X
2 8 X X X X
3 3 X X X1
4 3 X X X2
Notes
1. Port 3 must be used as a control port when port 1 is used as a latched and strobed input or a latched and strobed output port, 2. Port 4 must be used as a control port when port 2 is used as a latched and strobed input or a latched and strobed output port.
gain control of the bus, but does not restrict the speed at which faster modules can transfer data via the same bus. The most obvious applications for the master·slave capabilities of the !;Ius are multiprocessor configura·
tions, high speed direct·memory·access (OMA) opera·
tions and high speed peripheral control, but are by no means limited to these three.
Programmable Timer
The iSBC 80105 provides a fully programmable .binary 14-bit interval timer utilizing the Intel 8155 RAMIIOI Timer. The system designer simply configures the timer via software to meet system requirements. Whenever a given time delay is needed, software commands to the programmable timer select the desired function. Four functions are available as shown in Table 2. The con- tents of the timer counter may be read at any time dur- ing system operation.
Serial 1/0 Interface
The iSBC 80105 provides serial 1/0 capability through the serial input data (SID) and serial output data (SOD) func- tions'of the Intel 8085A CPU. These functions are con- trolled exculsively by software through execution of the 8085A RIM and SIM instructions. The baud rate for the serial 1/0 interface is determined by the system time available for execution of serial. 1/0 support software.
Hence, the maximum baud rate supported by the iSBC 80105 is solely dependent on the overall system real- time software requirements. Serial 1/0 signals are TTL compatible and sockets are provided on the board for optional connection of RS232C line drivers and receivers.
Interrupt Capability
The iSBC 80105 takes advantage of the powerful inter- rupt processing capability of the 8085A CPU. Interrupt requests are routed to the four interrupt inputs of the 8085A CPU (i.e., TRAP, RST 7.5, RST 6.5, and RST 5.5 in order of priority, TRAP highest), and each input gener- ates a unique memory address (I.e., TRAP: 2416, RST 7.5:
3C16, RST 6.5: 3416, RST 5:5: 2C16 ). Asingle 8085A jump
1-9
Table 2. Programmable Timer Functions Function
Programmable pulse
Square wave rate generator
Rate generator
Programmable strobe
Operation
Timer out goes low during the second half of count. Therefore, the count loaded in the count length register should be twice the pulse width desired.
Timer out will remain high until one- half the count has been completed, and go low for the other half of the count. The count length is auto- matically reloaded when terminal count is reached.
Divide by N counter. A repetitive timer out low pulse is generated and new timeout initiated every time ter- minal count is reached.
A single low pulse is generated upon reaching terminal count. This func- tion is extremely useful for genera- tion of real-time clocks.
instruction at each of these addresses then provides linkage to locate each interrupt service routine indepen- dently anywhere in memory. All interrupt inputs with the exception of one (TRAP) may be masked via software.
The trap interrupt should be used for conditions such as power-down sequences which require immediate atten- tion by the 8085A CPU.
Expansion Capabilities
Memory and 110 capacity may be expanded and addi- tional functions added using Intel MULTIBUS compati- ble expansion boards. High speed integer and floating- point arithmetic capabilities may be added by using the iSBC 310 High Speed Mathematics Unit. Memory may be expanded to 65,536 bytes by adding user specified combinations of RAM boards, EPROM boards, or com- binations boards.lnputloutput capacity may be increased by adding digital 1/0 and analog 1/0 expansion boards.
Mass storage capability may be achieved by adding sin-
gle or double density diskette controllers as subsys- tems. Modular expandable backplanes and card cages are avialable to support multi board systems.
Systems Development Capability
The development cycle of iSBC 80/05-based products may be significantly reduced using an Intellec micro- computer development system. The resident macro- assembler, text editor, and system monitor greatly simplify the design, development, and debug of iSBC 80/05 system software. An optional diskette operating system provides a relocating macroassembler, a relo- cating loader and linkage editior, and a library manager.
SPECIFICATIONS Word Size
Instruction - 8, 16, or 24 bits Data - 8 bits
Cycle Time
Basic Instruction Cycle - 2.03 1-'5, ± 0.1 % Note
Basic' instruction cycle is defined as the fastest instruction (i.e., four clock cycles).
Memory Addressing
ROMIEPROM - O-OFFFH RAM - 3EOO H
Memory Capacity
On·Board ROMIEPROM .,... 4K bytes (with Intel 2716) or 2K bytes (with I nte12708)
On·Board RAM - 512 bytes
Off·Board Expansion- Up to 65,536 bytes in user specified combination of RAM, ROM, and PROM
110 Addressing
On·Board Programmable 1/0 - see Table 1 Port 8155 8155 8155
8155 8155 Timer 8155 Timer Control Port 1 Port 2 Ports
Port Low·Order Hlgh·Order
3&4 Byte
Address 00 01 02 03 04
110 Capacity
Parallel - 22 programmable lines (see Table 1) Note
Byte 05
The iSBC SO/OS may be expanded to 1102 programmable input/output lines by using optional iSBC SO I/O boards.
Serial Communications Characteristics
SID and SOD functions of the8085A CPU are used for serial 1/0. They are controlled by software through RIM
A unique in-circuit emulator (ICE-85) option provides the capability of developing and debugging software direct- lyon the iSBC 80/05.
Programming Capability
PL/M-80 - Intel's high level programming language, PUM, is also available as a resident Intellec microcom- puter development system option. PUM provides the capability to program in a natural, algorithmic language and eliminates the need to manage register usage or allocate memory. PUM programs can be written in a much shorter time than assembly language programs for a given application.
and SIM instructions of the 8085A CPU. Baud rate is determined by system time available for serial 110 handl- ing. On-board timer may be used to greatly ease serial 1/0 timing requirements.
Interrupts
Four-level interrupt routed to8085A CPU interrupt inputs.
Each interrupt automatically vectors the processor to a unique memory location.
Interrupt Memory
Priority Type
Input Address
TRAP 24 16 Highest Non·maskable
RST 7.5 3C16
t
MaskableRST 6.5 34 16 Maskable
RST 5.5 2C16 Lowest Maskable
Timer
Input Frequency Reference - 122.88 kHz ± 0.1 % (8.14 I-'s period nominal)
Output Frequencles/Tlmlnglntervals
Function Timer/Counter
Min Programmable pulse 8.14 ~s Square wave rate generator 7.50 Hz
Rate generator 7.50 Hz
Programmable strobe S.14 ~s
Interfaces
Bus - All signals TTL compatible Parallel 1/0 - All signals TTL compatible
Max 66.67 ms 61.44 kHz 61.44 kHz 133.33 ms
Interrupt Request - All TTL compatible (active-low) Serial 1/0 - TTL; sockets available for RS232Cline drivers and receivers
System Clock (808SA CPU)
1.966 MHz ± 0.1%
iSBC 80/05
Interface Lines Centers Mating Connector (qty) (In.)
Bus 86 double·sided 0.156 Viking 2KH43/9AMK12 ParalielllO 50 double·slded 0.100 3M 3415·000
Molex 09·66·1071 Connector Molex 09·50·7071 Serial 110'
Connector 7 single·slded 0.156
AMP 87194·6 Connector AM P 3·87025·4
Connector Note
1. Connectors and pins from one vendor may only be used with connec- tors and pins from the same vendor.
Line Drivers and Terminators
1/0 Drivers - The following line drivers are all compati·
ble with the 110 driver sockets on the iSBC 80105' Driver Characteristic Sink Current (mA)
7438 I.OC 48
7437 I 48
7432 NI 16
7426 I,OC 16
7409 NI,OC 16
7408 NI 16
7403 I,OC· 16
7400 I 16
Note
I ~ Inverting; NI ~ non·invertlng; OC ~ open coliector.
1/0 Terminators - Intel provides 220Q/330Q divider and 1 kQ pull-up resistive terminator packs for termination 01110 nnes programmed as inputs. These options are as follows:
220Q
+5V---~~ __ - - - '
220QJ330Q.l . ~~. ---~----~o I$BC 901 OPTION
, kQ
1 kQ + 5V ---"VV'.~---_:_----<o ISBC 902 OPTION
Bus Drivers
Driver Characteristic Sink Current (mA)
Data Tri'stdle 50
Address Tri·state 50
Commands Trl'str'e 32
ORDERING INFORMATION Part Number
SBC 80105
Description
Single Board Computer
1·11
RS232C Drivers and Receivers
The following RS232C drivers and receivers are compati- ble with the RS232C socket on the iSBC 80105:
RS232C Driver- National DS1488 or TI SN7518B RS232C Receiver - National DS1490 or TI SN75189
Physical Characteristics
Width - 12.00 in. (30.49 cm) Height - 6.75 in. (17.15 cm) Depth - 0.50 in. (1.27 cm) Weight - 12.0 oz (339.8 gm)
Electrical Characteristics
DC Power Requirements
Voltage Without
PROM1 (:!:5'10)
(max) VCC~+5V ICC~ 1.80 mA
VDD~+12V4 IDD~O
VBB~ -5V 4 IBB~O VAA~ -12V 5 IAA~O Notes
With 2716 With 8708 EPROM2' EPROM3 (max) (max) 2.65A 2.45A 7 mAS 137 mA
a
90mA23 mAS 23 mAS
1. Does not include power required for optional EPROM/ROM, 110 drivers, ·and 110 terminators.
2. With two Intel 2716 EPROMs and 22012/33012 terminators instalied for 22 input ports; ~II, terminator inputs,low.
3. With two Intel 2708 EPROMs and 22012/33012 terminators instalied for 22 input ports; all terminator inputs low.
4. Required for 2708 EPROMs.
5. Required only when RS232C capabilily required.
Environmental Characteristics
Operating Temperature - 0 'C to
+
55 'C.. Reference Manual
9800483D - iSBC 80105 .Hardware Reference Manual (NOT SUPPLIED)
Reference manuals are shippedwith each product only if designated SUPPLIED (see above). Manuals may be ordered from any·'nte'sates representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
SINGLE BOARD COMPUTER
• Upward compatible with iSBC 80/10A Single Board Computer
• 8080A CPU used as central processing unit
• One iSBX bus socket for iSBX MULTIMODULE board expansion
• 1 K byte of readlwrite memory with sockets for expansion up to 4K bytes
• Sockets for up to 16Kbytes of read only memory
.48 programmable parallel 1/0 lines with sockets for interchangeable line drivers and terminators
• Programmable synchronous/asynchro·
nous communications interface with selectable RS232C or teletypewriter
comp~tibility
• Single level interrupt with 11 interrupt sources
• Auxiliary power bus and power.fail interrupt control logic for RAM battery backup
• 1.04·millisecond interval timer
• Limited master MUL TIBUS interface
The Intel® iSBC 80/10B board is a member of Intel's complete line of OEM microcomputer systems which take full advantage of Intel's LSI technology. to provide economical, self-contained computer-based solutions for OEM applications. The iSBC 80/10B board is a complete computer system on a single 6.75 x 12.00cinch printed circuit card. The CPU, system clock, iSBX bus interface, read/write memory, read only memory sockets, I/O ports and drivers, serial communications interface, bus control logic, and drivers all reside on the board.
'Same product, manufactured by Intel Puerto Rico, Inc.
iSBC 80/10B
FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel MOS 8D8DA CPU, fabricated on a single LSI chip, is the central processor for the iSBC 80./1 DB board. The 8D8DA contains six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs, providing both single and double precision operators. A block diagram of iSBC 8D/1DB board functional compo- nents is shown in Figure 1.
iSBX Bus MULTIMODULE Board Expansion
The new iSBX bus interface brings an entirely new dimension to system design offering incremental
RS232C COMPATIBLE
5 DATA/CON
INTER ERIAL TROl FACE
:0
.RS232C INTERFACE
TTY
0"'"'
DATA/CONTROL INTERFACE"TTY INTERFACE
lJ
BAUD RATE SELECTOR (JUMPERS)
on-board expansion with small iSBX boards. One iSBX bus connector interface is provided to accomplish plug-in expansion with any iSBX MUL TIMODULE board. iSBX boards are available to provide expansion equivalent to the I/O available on the iSBC 80./1 DB board or the user may configure entirely new functionality such as math directly on- board. The iSBX 350. programmable I/O MUL TI- MODULE board provides 24 I/O lines using an 8255A programmable peripheral interface. There- fore, the iSBX 350. module together with the iSBC 8D/1DB board may offer 72 lines of programmable 110. Alternately, a serial port may be added using the iSBX 351 serial I/O multimodule board or math may be configured on-board. with the iSBX 332 floating point math MUL TIMODULE board.
1.04 MSEC INTERVAL TIMER
POWER FAIL
USER DESIGNATED PERIPHERALS
· .... ~'~ .. :O
P~RALL,~L 110 LINES
ORIVERI TERMINATOR
INTERFACE
I j\
USER DESIGNATED Isex MUL TIMODULE
BOARD UI ARD
--,
~''"'cO "'""
'"f~~".:"" - ~~~
I I
I isex BUS I
I MUL TIMODULE I CONNECTOR I
l_--J+ __ /\
-'Yi~'
SELECTED7r7
INTERRUPT 3 1 1 1, . - - - ,[
I
INTERRUPT SELECTORJ
(JUMPERS)
\/ '7 \L
16K I[ 8 1K II: 8 RAM PROGRAMMABLE
8080A PROGRAMMABLE
ROM/EPROM (SOCKETS TO COMMUNICATIONS CPU PERIPHERAL
(SOCKETS) 4K II: 8) INTERFACE (USART) INTERFACES
0 {) ')
ON-BOARD SYSTEM BUSj) _rt
MULTIBUS
J
INTERFACE
\/ ..
MUL TIe US SYSTEM BUS
...
~Figure 1. iSBC 80/10B Single Board Computer Block Diagram 1·13
The iSBX board is a logical extension of the on- board programmable I/O and is accessed by the iSBC 80/10B single board computer as common I/O port locations. The iSBX board is coupled directly to the 8080A CPU and therefore becomes an integral element of the iSBC 80/10B single board computer providing optimum performance.
Memory Addressing
The 8080A has a 16-bit program counter which allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of read/write memory, may be used as a last-in/first-out storage area for the contents of the program counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls the addressing of this external stack. This stack provides subroutine nesting bounded only by memory size.
Memory Capacity
The iSBC 80/10B board contains 1 K bytes of read/write static memory. In addition, sockets for up to 4K bytes of RAM memory are provided on board. Read/write memory may be added in 1 K byte increments using two 1 Kx4 Intel 2114A-5 static RAMs. All on-board RAM read and write operations are performed at maximum processor speed.
Sockets for up to 16K bytes of nonvolatile read- only-memory are provided on the board. Read- only-memory may be added in 1 K byte increments up to 4K bytes (using Intel 2708, 2758, or 2608): in
2K byte increments up to 8K bytes (using Intel 2716 or 2316A): or in 4K byte increments up to 16K bytes (using Intel 2732). All on-board ROM or EPROM read operations are performed at maximum proces- sor speed.
Parallel I/O Interface
The iSBC 80/10B board contains 48 programmable parallel I/O lines implemented using two Intel 8255A programmable peripheral interfaces. The system software is used to configure the I/O lines in any combination of unidirectional input/output, and bidirectional ports indicated in Table
1.
There- fore, the I/O interface may be customized to meet specific peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for inter- changeable I/O line drivers and terminators. Hence, the flexibility of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity, and drive/termination .characteristics for each appli- cation. The 48 programmable I/O lines and signal ground lines are brought out to two 50-pin edge connectors that mate with flat cable or round cable.Serial I/O Interface
A programmable communications interface using the Intel® 8251A Universal Synchronous/Asyn- chronous Receiver/Transmitter (USART) is con- tained on the board. A jumper selectable baud rate
Table 1. Input/Output Port Modes of Operation Mode of Operation Unidirectional
Port Lines
Input
(qty) Output Bidirectional Control
Unlatched Latched &
Latched Latched &
Strobed Strobed
1 8 X X X X X
2 8 X X X X
3 8 X X X'
4 8 X X
5 8 X X
6 4 X X
4 X X
Notes
Port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output port or port 1 is used as a bidirectional port.
iSBC 80/10B
generator provides the USART with all common communications frequencies. The USART can be programmed by the system software to select the desired synchronous or asynchronous serial data transmission technique (including IBM Bi-Sync).
The mode of operation (i.e., synchronous or asyn- chronous), data format, control character format and parity are all under program control. The 8251A provides full duplex, double-buffered transmit and receive capability. Parity, overrun, and framing error detection are all incorporated in the USART.
The inclusion of jumper selectable TTY or RS232C compatible interfaces on the board, in conjunction with the USART, provides a direct interface to teletypes, CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems. The RS232C or TTY command lines, serial data lines, and signal ground lines are brought out to a 26-pin edge connector that mates with RS232C compat- ible flat or round cable.
Interrupt Capability
Interrupt requests may originate from 11 sources.
Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to be transferred to the CPU (i.e., input buffer is full) or a byte of information has been transferred to a peripheral device (i.e., output:buffer is empty).
Three jumper selectable interrupt requests can be automatically generated by the USART when a character is ready to be transferred to the CPU (i.e., receive channel buffer is full), a character is ready to be transmitted (i.e., the USART is ready to accept a character from the CPU), or when the transmitter is empty (i.e., the USART has no character to transmit). These five interrupt request lines are all maskable under program control. Two interrupt request lines may be interfaced directly to user designated peripheral devices; one via the MUL TI- BUS system bus and the other via the I/O edge connector. One jumper selectable interrupt request . may be interfaced to the power-fail interrupt control logic. One jumper selectable interrupt request may originated from the interval timer. Two general purpose interrupt requests are jumper selectable from the iSBX interface. These two signals permit a user installed MUL TIMODULE board to interrupt the 8D8DA CPU. The eleven interrupt request lines share a single CPU interrupt level. When an interrupt request is recognized, a restart instruction (RESTART 7) is generated. The processor responds by suspending program execu- tion and executing a user defined interrupt service routine originating at location 381,6.
1·15
