1988 HANDBOOKS

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1988 HANDBOOKS

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About Our Cover:

The microprocessor has changed the way we work and live. Future generations will equate its impact on society with that of the invention of the wheel. Like the hub of a wheel, the processor stands at the center, but its potential is realized only when coupled with carefully matched peripheral devices. With this in mind, Intel

intJ

Intel the Microcomputer Company:

When Intel invented the microprocessor in 1971, it created the era of microcomputers. Whether used as microcontroIJers in automobiles or microwave

ovens, or as personal computers or supercomputers, Intel's microcomputers have always offered leading-edge technology. In the second half of the 1980s, Intel architectures have held at least a 75% market share of microprocessors at 16 bits and above.

Intel continues to strive for the highest standards in memory, microcomputer components, modules, and systems to give its customers the best possible competitive advantages.

MICROPROCESSOR AND PERIPHERAL HANDBOOK VOLUME I MICROPROCESSOR

1988

which may appear in this document nor does it make a commitment to update the information contained

herein: . . .. . ,;. . .

Intel retai~s the right to make changes to these specifications at any time, without notice.

Contact· your Ibcal sales office to obtain the latest specifications before placing your order.

The following are trademarks of Intel Corporation and may only be used to identity Intel Products:

Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, GENIUS, i,

t,

ICE, iCEL, iCS, iDBP, iDIS, 1²1CE, iLBX, im, iMDDX, iMMX, Inboard, Insite, Intel, intel, intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME, MUL TIBUS, MULTICHANNEL, MUL TIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical suffix, 4-SITE.

MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation.

*MUL TIBUS is a patented Intel bus.

Additional copies of this manual or other Intel literature may be obtained from:

Intel Corporation Literature Distribution Mail Stop SC6-59 3065 Sowers Avenue Santa Clara, CA 95051

@INTELCORPORATION 1987

CUSTOMER SUPPORT

CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with hardware support, software support, customer training, network support, and consulting services. For more information contact your local sales offices.

After a customer purchases any system hardware or software product, service and support become major factors in determining whether that product will continue to meet a customer's expectations. Such support requires an inter- national support organization and a breadth of programs to meet a variety of customer needs. As you might expect, Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices providing hardware repair services, software support services, customer training classes, and consulting services.

HARDWARE SUPPORT SERVICES

Intel is committed to providing an international service-support package through a wide variety of service offerings available from Intel Hardware Support.

SOFTWARE SUPPORT SERVICES

Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshooting guides and COMMENTS Magazine). Basic support includes updates and the subscription service. Contracts are sold in environments which represent product groupings (i.e., iRMX environment).

CONSULTING SERVICES

Intel provides field systems engineering services for any phase of your development or support effort. You can use our systems engineers in a variety of ways ranging from assistance in using a new product, developing an applica- tion, personalizing training, and customizing or tailoring an Intel product to providing technical and management consulting. Systems Engineers are well versed in technical areas such as microcommunications, real-time applica- tions, embedded microcontrollers, and network services. You know your application needs; we know our products.

Working together we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING

Intel offers a wide range of instructional programs covering various aspects of system design and implementation.

In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.

For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our workshops to you for on-site instructions. Covering a wide variety of topics, Intel's major course categories include:

architecture and assembly language, programming and operating systems, bitbus and LAN applications.

Table of Contents

Alphanumeric Index ... . . . • . . . vi CHAPTER 1

Overview

Introduction ...•... :... 1-1 CHAPTER 2

8086, 8088 Microprocessor Family DATA SHEETS

8086 16-Bit HMOS Microprocessor. . . .. . . .. . . .. . . . .. . . .. . .. . . 2-1 80C86A 16-Bit CHMOS Microprocessor. . . • . . . 2-31 80C86AL 16-Bit CHMOS Microprocessor. . . 2-60 8088 8-Bit HMOS Microprocessor. . . 2-89 80C88A 8-Bit CHMO$ Micropro.cessor . . . .. 2-119 80C88AL8-Bit CHMOS Microprocessor. . . .. . . .. .. . . .. . . . .. 2-151

8087/8087-2/8087-1 Numeric Data Coprocessor... 2-183

82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors ... 2-205 82C88 CHMOS Bus Controller. . . .. . . .. 2-214

8289/8289-1 Bus Arbiter... 2-222

8237 A High Performance Programmable DMA Controller

(8237A, 8237A-4, 8237A-5) ... 2-234 82C37 A-5 CHMOS High Performance Programmable DMA Controller. . . .. 2-253 8259A18259A-2/8259A-8 Programmable Interrupt Controller. . . .. 2-271 82C59A-2 CHMOS Programmable Interrupt Controller ... 2-295 82261 CMOS Multi-Function LSI Peripheral ... " . . . .. 2-315 CHAPTER 3

80286 Microprocessor Family DATA SHEETS

80286 High Performance Microprocessor with Memory Management and

Protection. . . 3-1 80287 80-Bit HMOS Numeric Processor Extention : . . . 3-56 82258 Advanced Direct Memory Access Coprocessor ... 3-82 82C288 Bus Controller for 80286 Processors

(82C288-12, 82C288-10, 82C288-8) ... 3-141 82C284 Clock Generator and Ready Interface for 80286 Processors

(82C284-12, 82C284-10, 82C284-8) . . . .. 3-162 CHAPTER 4

80386 Microprocessor Family

80386 High Performance Microprocessor with Integrated Memory Management. . . 4-1 80387 80-Bit CHMOS III Numeric Processor Extension with Integrated System.... 4-129 82380 High Performance 32-Bit DMA Controller wI Integrated System

Support Peripherals ... 4-166 82385 High Performance 32-Bit Cache Controller ... 4-287 CHAPTERS

Graphics Coprocessor Family

82716IVSDD Video Storage and Display Device ... 5-1

82786 CHMOS Graphics Coprocessor. . . 5-34

AP-268 Low Cost and High Integration Graphics System Using 82716... 5-77

AP-270 82786 Hardware Configuration.. . .. . . .. .. . . .. . . . ... 5-129

AP-409 Interfacing an 82786 Based Graphics Board to the IBM PCI AT. . . .. 5-190

AP-408 An Introduction to Programming the 82786 Graphics Coprocessor. . . .. 5-216

Alphanumeric Index

80C86A 16-Bit CHMOS Microprocessor... 2-31 80C86AL 16-Bit CHMOS Microprocessor ... , . . . 2-60 80C88A 8-Bit CHMOS Microprocessor.. .. . . .. . . .. . . .. . . .. . . .. 2-119 80C88AL 8-Bit CHMOS Microprocessor ... ,... 2-151 80286 High Performance Microprocessor with Memory Management and Protection. . . 3-1 80287 80-Bit HMOS Numeric Processor Extention ... . 3-56 80386 High Performance Microprocessor with Integrated Memory Management... 4-1 80387 80-Bit CHMOS III Numeric Processor Extension with Integrated System... 4-129 808616-Bit HMOS Microprocessor... 2-1 8087/8087-2/8087-1 Numeric Data Coprocessor. . . .. . . .. 2-183 8088 8-Bit HMOS Microprocessor. . . 2-89 82C284 Clock Generator and Ready Interface for 80286 Processors

(82C284-12, 82C284-10, 82C284-8) . . . .. .. . .. . . .. .. . . .. 3-162

82C288 Bus Controller for 80286 Processors

(82C288~12,

82C288-1 0, 82C288-8) . . . .. 3-141

82C37 A-5 CHMOS High Performance Programmable DMA Controller ... 2-253

82C59A-2 CHMOS Programmable Interrupt Controller. . . .. 2-295

82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors. . . .. 2-205

82C88 CHMOS Bus Controller. . . .. . . .. . . .. 2-214

82258 Advanced Direct Memory Access Coprocessor . . . 3-82

'82261 CMOS Multi-Function LSI Peripheral ...•...• :.... 2-315

8237 A High Performance Programmable DMA Controller (8237 A, 82!37 A-4, 8237 A-5) . . . .. 2-234

82380 High Performance 32-Bit DMA Controller wi Integrated System Support Peripherals 4-166

82385 High Performance 32-Bit Cache Controller . . . .. 4-287

8259A18259A-2/8259A-8 Programmable InterruptCQntrolier. . .... . . . .. . . .. 2-271

82716IVSDD Video Storage and Display Device... 5-1

82786 CHMOS Graphics Coprocessor. . . 5-34

8289/8289-1 Bus Arbiter ..••... ;... 2-222

Overview 1

inter

^OVERVIEW

INTRODUCTION

Intel microprocessors and peripherals provide a complete solution in increasingly complex application environ- ments. Quite often, a single peripheral device will replace anywhere from 20 to 100 TTL devices (and the associated design time that goes with them).

Built-in functions and standard Intel microprocessor/

peripheral interface deliver very real time and perfor- mance advantages to the designer of microprocessor- based systems.

REDUCED TIME TO MARKET

When you can purchase an off-the-shelf solution that replaces a number of discrete devices, you're also replac- ing all the design, testing, and debug time that goes with them.

INCREASED RELIABILITY

At Intel, the rate offailure for devices is carefully tracked.

Highest reliability is a tangible goal that translates to higher reliability for your product, reduced downtime, and reduced repair costs. And as more and more functions are intergrated on a single VLSI device, the resulting system requires less power, produces less heat, and requires fewer mechanical connections-again re- sulting in greater system reliability.

LOWER PRODUCTION COST

By minimizing design time, increasing reliability, and

replacing numerous parts, microprocessor and peripheral solutions can contribute dramatically to lower product costs.

HIGHER SYSTEM PERFORMANCE

Intel microprocessors and peripherals provide the highest system performance for the demands of today's (and tomorrow's) microprocessor-based applications. For exam- ple, the 80386 32 bit offers the highest performance for multitasking, multiuser systems. Intel's peripheral pro- ducts have been designed with the future in mind. They support all of Intel's 8, 16 and 32 bit processors.

HOW TO USE THE GUIDE

The following application guide illustrates the range of microprocessors and peripherals that can be used for the applictions in the vertical column of the left. The peripherals are grouped by the I/O function they control.

CRT datacommunication, universal (user programmable), mass storage dynamic RAM controllers, and CPU/bus support.

An "X" in a horizontal application row indicates a potential peripheral or CPU, depending upon the features desired. For example, a conversational terminal could use either of the three display controllers, depending upon features like the number of characters per row or font capability. A "Y" indicates a likely candidate, for example, the 8272AFloppy Disk Controller in a small business computer.

The Intel microprocessor and peripherals family provides a broad range of time -saving, high performance solutions.

APPLICATION CHART

POTENTIAL ~PP.LICATION X - TYPICAL APPLICATION Y

NUMERIC

...

_:II:

APPLlCAl:lON MICROPROCESSORS PROCESSORS SUPPORT DMA

M

^DRAM

"

'~. ,I,

"

; ^m _i

^:z:

B 5 ^B

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^:= D i I I ^:a .. _8i

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^~

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I

Ii Ii

iii iii i ^fj

i:I i:I i:I

~

^i:I

~ i:l

i:I

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i:I PERIPHERALS

'x,

Printers X X. X ^y X X X X Y Y X ^X· X X X X X

Plotters X X X X X Y X X Y X X X X X X X X

Keyboards X 'Y X X

MASS STORAGE

Hard Disk' 'j( X X X· ^{y y} X X Y ^y

Mini Winchester X X y y y y

Tape X Y X ^{:Y' y' :}

Cassette y y X y

Floppy/Mini V y y

COMMUNICATIONS Digital Telephone

ISDN y,

PBX X "X y y X, X X X ^.y, X Y ^y V X .X X X

LANs X X X X X Y Y X X ^y X 'y X X

Modems X X X

Bisync X X

SOlC/HOlC X X

Senal Backplane Y X X X

Central Office ^" :'X X X y V X X X ^y X X Y ^{y y} X X X X

Network Control .'. ^y X y y X X Y X y Y X Y X X X X

OFFICE/BUS

'Copier/FAX X X X y X Y X X X X X X X X

Wordprocessor X X' X X ,X X V Y V ^y V X Y y' _Y y X X X X

Typewnter X Y Y Y X X X X X

ElectroniC Mall X X X X y V X 'X X X X X X

Transaction System y X X X X X X Y Y X X Y X X X X X X

Data Entry X X X. X X X V ^y X V ,~ X X X ,X X

COMPUTERS

Small BUSiness Computer X :X .y X X ^{.y y y y} V V V X Y X X Y X y ⁾⁽ X, X X

PC y y y y X X Y y X X y y y X y y y X Y X X X X

Portable PC' Y

."

^{x X}

^x

^X

^x

^{y v y}

^x

^{y y x X X X X'}

Home Computer X X X X Y ~ ^{.X X Y Y} y X Y Y X X X X X

TERMINALS

ConversatIOnal y y y X X X X

Graphl,cs CRT

X Y Y Y

~

^{.X Y y Y y y V X y X X X X X}

Editing X ,X X X X X Y Y Y Y Y X X X X X

Intelligent X X I< X Y ^y X ^{y y y} X y Y X X X X X

Integrated Voice/Data X X X X X

Vld,eotex X X X X X 'X X Y ^{y y y} y X X X X X

Pnntlng Laser, Impact X X X X X X X X X y Y Y Y v X X X X X X

Portable X Y X Y Y X ^y y y y X ⁾⁽ X

INOUSTRIAUAUTO

'y

RobotICs Y X Y ^{y y y l(} Y X X l! X X y X Y X X

Network X X X X X X X Y Y X X Y Y X Y X X

NUrT)enc Cqntrol X X X X Y V V V X V X X X X Y X y X X

Process Control X X X X X Y X Y Y Y y X X X X Y X X X X Y X Y X X

Instrumentation X X X X X X X X ,X- _X X. ,X X X Y X X X X X X X

AViation/Navigation X X X X X X Y Y Y X X X Y X X Y X X X X

INDUSTRIAl/DATA ACQUISITION

Laboratory InstrumentatIOn X X X X Y X X X X X Y X X X X X X X

Source Data X X ^y X X ,X X V X X X X

Auto Test X X X X· Y X Y X X X Y X X X X X X X

MedICal X X X ,X Y X X 'X 'I Y 'Y X X y X X X X X X X

Test Instruments X X X X Y X X X Y Y Y X X Y X X X Y X X X X X Secunty

COMMERCIAL DATA PROCESSING ~ X V X Y X X V X X X V X Y X X

POS Terminal X X X X X X X X X X Y X X X X X X

FinanCial Transfer X X X 'Y X Y Y Y X X X Y X X X X X X X

AutomatIC Teller X X ,)\ Y X X X, _V X X X X

Document Processing X X X X X Y X X X X Y X X X X

WORKSTATIONS

OffICe X X X X X Y y y y y X X Y X y y X X Y X Y X X

Engineering X X X Y' y y y y _X X· V X If y v ^{y y} X Y X ⁾⁽

CAD X Y Y Y Y Y X X Y Y Y Y Y Y Y X X

MINI MAINFRAME

Processor & Control Store X X Y Y Y X Y Y X Y Y X Y X X

Data Base Subsystems X X y y y y y y y y y y y X X

1/0 Subsystems Y Y Y Y Y Y Y Y Y X Y X X

Communication Subsystem X X Y Y ^{y y y} X Y y X Y X X

APPLICATION CHART

POTENTIAL APPLICATION X - TYPICAL APPLICATION Y

SPECIAL LOCAL

PERIPHERAL DISK AREA

DISPLAY CbNTROL CONTROL DATA COMMUNICATIONS NETWORKING TELECOMMUNICATIONS APPLICATION

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Y ,y X ^'J( X X X X X ,

X ^{)t, Printers}

y X X X X X Plotters

)( V X ^{" Keyboards}

MASS STORAGE

X ^y Hard Disk

y MIni Winchester

X ^{}( Tape}

X Cassette

y, Y' "

:",

Floppy/Mini

COMMUNICATIONS

, ^"', Y X V y Digital Telephone

X y X Y Y Y ISDN

X X X X X X X 'Y' X ^{y y} y X, PBX

Y X X X X X X y X X LANs

X X X X X- X X "X, " V Modems

X X X Bisync

V X X 'X ' X V SDLC/HDLC

y X X X X X X X X Serial Backplane

X X X X X X X V X X V Central OffICe

y X X X X X X Network Control

OFFICE/BUS

y X X X X X X X X X Y Y Copler/FAX

X X ^y Y ^y " X' ,X _, .. ^", ';> y Wordprocessor

X X X X X X X X X X X y TypeWriter

X X X X ^~V X ElectronIC Mall

X X X X Y y Transaction System

X X X, X X ^{J( y} V Data Entry

COMPUTERS

X X X Y Y V X X X X X )1" X, Small BUSiness Computer

X X X X X X Y Y Y X X X X X X X X Y y PC

X X X X Y y X X X

" ,X X ^y, 'Y Portable PC

X X Y Y X X Y y Home Computer

,

,

^TERMINALS

X y X X X y y Conversational

y X X X X X X X X X X, GraphICs CRT

y X X X X X X X X X X Y Y Editing

Y X X X X X ,X X X X 'X X X X ^y Y Intelligent

X X y X y Y y Integrated VOice/Data

V X X X ^X, V Y Videotex

y X X X X X X X X X Y X X X X X Printing' Laser, Impact

V X X X X X y y Portable

INDUSTRIAUAUTO

,X V X V X X X RobotICS

y X X X X X X X Network

J( y X X X X X ^, X NumeriC Control

X y _{X X} X X X X X X Precess Control

X X V X X X X ^, \' ^' InstrumentatIOn

X X X X AViatIOn/NavigatIOn

" INOUSTRIAUDATA ACQUISITION

Y X Y X X X X Y Laboratory Instrumentation

X V Source Data

y X Y X X X Auto Test

,V X, _{Y X} X X X X X MedICal

y X Y X X X X X X X X Test Instruments

, v ~ , ,'I X ^{y If X X X .X X X} X ^Security

COMMERCIAL DATA PROCESSING

X X X X X X X X • X X, X X X ^y V POS Terminal

X y X Y X X X X Y FmanCial Transfer

I";

X ^y. .y X X ,V· ' V Automatic Telier

~ y y X X X Document Processing

WORKSTATIONS

y X X X y y y X X X X X X X ^X X y Office

X ^,X 'X Y y 'V X X X X X X 'X, X X Engineering

X y Y Y X X X X X X X CAD

MINI MAINFRAME

Y X X X X X X Processor & Control Store

X X X Data Base Subsystems

X X X X X X X X X 1/0 Subsystems

X X X X X X X X X Y X Communication Subsystem

CACHE MEMORY

01n1011987

Get Your Kit Together!

Intel's Microsystem Components Kit Solution

CPU

~i 8088/80C88 8086180C86 80168 80186

,

80268 80368 e"" eW,"" ce

,

i

NUMERIC PROCESSORS 8087 80287 80387

CPU SUPPORT 8231A 6253 8254/82C54 8255A182C55A 8256AH 6259A 6279 82389

DMA 8237 82285 82380 ' 62560

MEMORY SUPPORT 8203 6206 6207 82C08

CRT CONTROL 8275 8276 82716 82786

SPECIAL PERIPHERAL CONTROL

UPI~ 8041A18741A UPI'· 8042/8742 UPI ,. 80/83/87C452

•

•

• •

•

eo HARD COPY

; CONTROL e; UPI ,. 8042/8742

KEYBOARD

..

^{i, CONTROL 8279·5 UPI ,. 8042/8742}

FLOPPY DISK

•

^{C;ONTROL 8272A 82072 'c "} ""'liV'-,+'

..

^{, c , , , HARD DISK CONTROL 82064 ~} W>, " "

GLOBAL COMMUNICATIONS

•

^{8251A 82050 82510 8273 8274} 8291 Al92194 82530 80441834418744

• •

LOCAL AREA NETWORKING 82C501 82502 82586

•

82588 82590/92 iMCC

INSTRUMENTATION BUS (GPIB) 8291 8292

TELE-

X

COMMUNICATIONS '

29C13/C14/C16/C17

...: 29C48 ...: e

""IIIIIIIP9'"

~~~~OAlC51

""IIIIIIIP9"

^{e e}

29C53

II

ISP188

': 89024 , ,

1-..,...,.,0:-,----'

October 1987 Order Number 230664-006

8086, 8088 Microprocessor 2

Family

inter ₈₀₈₆

•

•

•

• •

•

16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1*

Direct Addressing Capability 1 MByte • Range of Clock Rates:

of Memory 5 MHz for 8086,

Architecture Designed for Powerful 8 MHz for 8086-2, Assembly Language and Efficient High 10 MHz for 8086-1

Level Languages • MUL TIBUS® System Compatible

14 Word, by 16-Blt Register Set with Interface

Symmetrical Operations • Available in EXPRESS

24 Operand Addressing Modes - Standard Temperature Range - Extended Temperature Range Bit, Byte, Word, and Block Operations

Available in 40-Lead Cerdlp and Plastic

•

8 and 16-Blt Signed and Unsigned Package

Arithmetic In Binary or Decimal

(See Packaging Spec. Order #231369)

Including Multiply and Divide

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5,8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.

'Changes from the 1985 handbook specification have been made for the 8086·1. See A.C. Characteristics TGVCH and TCLGL.

EXECUTION UNIT REGISTER FilE

DATA POINTER AND

INDEX REGS (8 WORDS)

16 BIT AlU

flAGS

BUS INTERFACE UNIT

I RELOCATION I

REGISTER FILE

BUS INTERFACE

UNIT

6·BYTE INSTRUCTION

QUEUE

HST--_r---~~---, I H T _

N M I - - -

CONTROL & TIMING

H O l D - -

HLOA ~-,..-r--...,...--"T""--...,...--~

cue: RESET READy GND Vee

SHE/57 .,g1S(,

• ,;'53

Figure 1.8086 CPU Block Diagram ^231455-1

AD • FiQ/GiO (HOLD)

52 (MliO)

AD' lOT/A)

(DEN)

AD. (ALE)

NMI (INTA)

eLK

231455-2

40 Lead Figure 2. 8086 Pin

Configuration

November 1986

8086

Table 1. Pin Descrlpt,lon

The following pin function descriptions are for 8086 sYstel11$ in either-:mil1imum or maximum mode. The "Local Sus" in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus, buffers).

Symbol Pin No. Type Name and Function

AD15-AD

o

^{2-16.39 I/O} ADDRESS DATA BUS: These lines constitute the time multiplexed' memory 110 address (T 1). and data (T 2. T 3. T W. T 4) bus.

Ao

is analogous to BHE for the lower byte of the data bus, pins D7-DO' It is lOW during T 1 when a byte is ,to be transferred on the lower portion of the bus in memory or I/O oper'ations. Eight-bit oriented devices tied to the lower half would normally use

Ao

to condition chip select functions. (See BHE.) These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus "hold acknowledge':'.

A19/SS. 35-38 0 ADDRESS/STATUS: During T 1 these are the four most significant A18/S5. address lines for memory operations. During 110 operations these A17/S4. lines are lOW. During memory and 110 operations. status information A1e/S3 is available on these lines during T 2, T 3. T

w.

T 4. The status of, the

interrupt enable FLAG bit (S5) is updated at the beginning of each' elK cycle. A17/S4 and A1e/S3 are encoded as shown.

This information ,indicates which relocation register is presently being used for data accessing.

These lines float to 3-state OFF during local bus "hold acknowledge."

A17/S4 A1S/SS Characteristics

o

(lOW) 0 Alternate Data

0 1 Stack

1 (HIGH) 0 Code or None

1 1 Data

Se isO ,

(lOW)

BHE/S7 34 0 BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus. pins D15-D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T 1 for read. write. and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T 2.

T 3. and T 4. The signal is active lOW. and floats to 3-state OFF in

"hold". It is lOW during T 1 for the first interrupt acknowledge cycle.

BHE

Ao

Characteristics

0 0 Whole word

0 1 Upper byte from/to odd address

1 0 lower byte from/to even address

1 1 None

RD 32 0 READ: Read strobe indicates that the processor is performing a memory of I/O read cycle. depending on the state of the S2 pin. This Signal is used,to read devices which reside on the 8086 local bus. RD is active lOW during T 2. T 3 and T

w

of any read cycle. and is guaranteed to remain HIGH in T 2 until the 8086 local bus has floated.

This signal floats to 3-state OFF in "hold acknowledge".

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

READY 22 I READY: is the acknowledgement from the addressed memory or 110 device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

TEST 23 I TEST: input is examined by the "Wait" instruction. If the TEST input is lOW execution continues, otherwise the processor waits in an "Idle"

state. This input is synchronized internally during each clock cycle on the leading edge of ClK.

NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from lOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

RESET 21 I RESET: causes the processor to imr"!1ediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the Instruction Set description, when RESET returns lOW. RESET is internally synchronized.

ClK 19 I CLOCK: provides the basic timing for the processor and bus controller.

It is asymmetric with a33% duty cycle to provide optimized internal timing.

Vee 40 Vee:

+

5V power supply pin.

GND 1,20 GROUND

MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are discussed in the following sections.

The fol/owing pin function descriptions are for the 808618288 system in maximum mode {Le., MNIMX = V ssJ.

Only the pin functions which are unique to maximum mode are described; aI/ other pin functions are as

described above. . -

82,S1, So 26-28 0 STATUS: active during T 4, T 1, and T 2 and is returned to the passive state (1. 1, 1) during T 3 or during T

w

when READY is HIGH. This status is used by the 8288 Bus Controller to generate all memory and I/O access control signals. Any change by S2.

51.

or

So

during T 4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T 3 or T

w

is used to indicate the end of a bus cycle.

8086

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

Si,S1,So

26-28 0 These signals float to 3-state OFF In "hold acknowledge". These status

(Continued) lines are encoded as shoWn.

S2

51 10·

Characteristics

o

(lOW) 0 0 Interrupt Acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1 (HIGH) 0 0 Code Access

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

RQ/G'To,

30,31 I/O REQUEST/GRANT: pins are used by other local bus masters to force

RQ/G'T1

the processor to release the local bus at the end of the processor's

current bus ~e. Eac~n is bidirectional with

RQ/GTo

having higher priority than

a/G'i" 1. /G'i"

pins have internal pull-up resistors and may be left unconnected. The request/grant sequence is as follows . (see Figure 9):

1. A pulse of 1 ClK wide from another local bus master indicates a local bus request ("hold") to the 8086 (pulse 1).

2. During aT 4 or T

1

clock·cycle; a pulse 1 ClK wide from the 8086 to

·the requesting master (pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter the "hold acknowledge" state at the next ClK. TheCPU's bus interface unit is disconnected logically from the local bus during "hold acknowledge".

3. A pulse 1 ClK wide from the requesting master indicates to the 8086 (pulse 3) that the "hold" request is about to end and that the 8086 can reclaim the local bus at the next ClK.

..

Each master-master exchange of the local bus is a sequence of 3 pulses. There must be dne dead ClK cycle after each bus exchange.

Pulses are active lOW.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during T 4 of the cycle when all the following conditions are met:

1. Request occurs on or before T 2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruCtion ·is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

lOCK 29 0 LOCK: output indicates that other system bus masters are not to gain control of the system bus while lOCK is active lOW. The lOCK signal . is activated by the "lOCK" prefix instruction and remains active until the

completion of the next instruction. This signal is active lOW, and floats to 3-state OFF in "hold acknowledge". '

infef ⁸⁰⁸⁶

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

QS1, QSo 24,25 0 QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is performed.

QS1 and QSo provide status to allow external tracking of the internal 8086 instruction queue.

QS1 QSo Characteristics

o

(LOW) 0 No Operation

0 1 First Byte of Op Code from Queue

1 (HIGH) 0 Empty the Queue

1 1 Subsequent Byte from Queue

The fol/owing pin function descriptions are for the 8086 in minimum mode (Le., MN/MX

= Vcd

Only the pin functions which are unique to minimum mode are described; aI/ other pin functions are as described above.

MilO 28 0 STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a memory access from an 1/0 access. MilO becomes valid in the T 4 preceding a bus cycle and remains valid until the final T 4 of the cycle (M

=

HIGH, 10

=

LOW). MilO floats to 3-state OFF in local bus "hold acknewledge" .

WR 29 0 WRITE: indicates that the precesser is perferming a write memery er write 1/0 cycle, depending en the state ef the MilO signal. WR is active fer T 2, T 3 and T

w

of any write cycle. It is active LOW, and floats to. 3-state OFF in lecal bus "held acknowledge".

INTA 24 0 INTA: is used as a read strebe fer interrupt acknewledge cycles. It is active LOW during T 2, T 3 and T

w

ef each interrupt acknewledge cycle.

ALE 25 0 ADDRESS LATCH ENABLE: previded by the precessor to latch the address into the 8282/8283 address latch. It is a HIGH pulse active during T 1 ef any bus cycle. Nete that ALE is never fleated.

DT/R 27 0 DATA TRANSMIT/RECEIVE: needed in minimum system that desires to.

use an 8286/8287 data bus transceiver. It is used to centrol the directien ef data flew through the transceiver. Legically DT

IR

is ~uivalent to S1 in the maximum mode, and its timing is the same as fer MilO. (T

=

HIGH, R

=

LOW.) This signal fleats to. 3-state OFF in local bus "held acknewledge".

DEN 26 0 DATA ENABLE: previdedas an eutput enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memery and 1/0 access and fer INTA cycles. Fer a read er INTA cycle it is active frem the middle ef T 2 until the middle of T 4, while fer a write cycle it is active from the beginning of T 2 until the middle ef T 4. DEN floats to 3- state OFF in lecal bus "held acknewledge".

HOLD, 31,30 1/0 HOLD: indicates that anether master is requesting a lecal bus "held." To. be HLDA acknewledged, HOLD must be active HIGH. The precesser receiving the

"hold" request will issue HLDA (HIGH) as an acknewledgement in the middle ef aT 1 cleck cycle. Simultaneeus with the issuance of HLDA the precesser will float the lecal bus and contro.l lines. After HOLD is detected as being LOW, the precesser will LOWer the HLDA, and when the precessor needs to. run another cycle, it will again drive the lecal bus and contro.l lines.

The same rules as for RQ/GT apply regarding when the local bus will be released.

HOLD is net asynchroneus input. External synchrenization sheuld be previded if the system cannot etherwise guarantee the setup time.

inter ⁸⁰⁸⁶

FUNCTIONAL DESCRIPTION General Operation

The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block dia- gram of Figure 1.

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the func- tions related to instruction fetching and queuing, op- erand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruc;tion stream queuing mechanism allows the BIU to keep the memory utilized very efficiently.

Whenever there is space for at least 2 bytes in the queue, the BIU will attempt a word fetch memory cycle. This greatly reduces "dead time" on the memory bus. The queue act,s as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BIU queue and provides un-relocated oper- and addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results·to the BIU for storage. See the Instruction Set description for further register set and architectural descriptions.

MEMORY ORGANIZATION

The processor provides a 20-bit address to memory which locates the byte being referenced. The memo- . ry is organized as a linear array of up to 1 million

Memory Segment Register Reference Need Used

bytes, addressed as OOOOO(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries.

(See Figure 3a.)

All memory references are made relative to base ad- dresses contained iri high speed segment registers.

The segment types were chosen based on the ad- dressing needs of programs. The segment register to be selected is automatically chosen according to the rules of the following table. All information in one segment type share the same logical attributes (e.g.

code or data). By structuring memory into relocat- able areas of similar characteristics and by automati- cally selecting segment registers, programs are shorter, faster, and more structured.

Word (16-bit) operands can be located on even or odd address boundaries and are thus not con- strained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most signifi- cant byte in the next higher address location. The BIU automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the software. This performance penalty does not occur for instruction fetches, only word operands.

Physically, the memory is organized as a high bank (D15-D8) and a low bank (D7-DO) of 512K 8-bit bytes addressed in parallel by the processor's ad- dress lines A19-A1. Byte data with even addresses is transferred on the D7-DO bus lines while odd ad- dressed byte data (Ao HIGH) is transferred on the D15-D8 bus lines. The processor provides two en- able signals, BHE and Ao, to selectively allow read- ing from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as nec- essary. '

Segment Selection Rule Instructions CODE (CS) Automatic with all instruction prefetch.

Stack STACK (SS) All stack pushes and pops. Memory references relative to BP base register except data references.

Local Data DATA (DS) Data references when: relative to stack, destination of string operation, or explicitly overridden.

External (Global) Data EXTRA (ES) Destination of string operations: explicitly selected using a segment override.

intJ ⁸⁰⁸⁶

.r---J. FFFFFH

f D } C O D E SEGMENT ,--_----L--, XXXXOH

t---

i F =

}STACKSEGMENT +OFrSET

SEGMENT

tll

~R~E~G'~S~I;R~F~'L~E ~~-~:-~=l' I

DATA SEGMENT

f - - -

}EXTRA DATA SEGMENT '----I--~

~OOOOOH 231455-3

Figure 3a. Memory Organization In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd ad- dress, respectively. Consequently, in referencing word operands performance can be optimized by lo- cating data on even address boundaries. This is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt pro- cessing or task multiplexing.

RESET BOOTSTRAP PROGRAM JUMP

INTERRUPT POINTER FOR TYPE 255

. .

INTERRUPT POINTER FOR TYPE 1 INTERRUPT POINTER

FOR TYPE 0

FFFFFH FFFFOH

3FFH 3FCH

7H

4H 3H 0 H

231455-4

Figure 3b. Reserved Memory Locations Certain locations in memory are reserved for specific CPU operations (see Figure 3b). locations from

address FFFFOH through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will al- ways begin execution at location FFFFOH where the jump must be. locations OOOOOH through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset ad- dress. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts.

MINIMUM AND MAXIMUM MODES

The requirements for supporting minimum and maxi- mum 8086 systems are sufficiently different that they cannot be done efficiently with 40 uniquely de- fined pins. Cons~ently, the 8086 is equipped with a strap pin (MN/MX) which defines the system con- figuration. The definition of a certain subset of the pins changes dependent on the condition of the strap pin. When MN/MX pin is strapped to GND, the 8086 treats pins 24 through 31 in maximum mode.

An 8288 bus controller interprets status information coded into So, S2, S2 to generate bus timing and control signals compatible with the MUl TIBUS® ar- chitecture. When the MN/MX pin is strapped to Vee, the 8086 generates bus control signals itself on pins 24 through 31, as shown in parentheses in Figure 2.

Examples of minimum mode and maximum mode systems are shown in Figure 4.

BUS OPERATION

The 8086 has a combined address and data bus commonly referred to as a time multiplexed bus.

This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package. This "local bus" can be buffered directly and .used throughout the system with address latching provided on memory and 110 modules. In addition, the bus can also be demulti- plexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system .

Each processor bus cycle consists of at least four ClK cycles. These are referred to as T 1, T 2, T 3 and T 4 (see Figure 5). The address is emitted from the processor during T 1 and data transfer occurs on the bus during T 3 and T 4. T 2 is used primarily for chang- ing the direction of the bus during read operations. In the event that a "NOT READY" indication is given by the addressed device, "Wait" states (T w) are in- serted between T 3 and T 4. Each inserted "Wait"

state is of the same duration as a ClK cycle. Periods

inter ⁸⁰⁸⁶

Vee

lUi

, _",CLOCK MNIMX Vee GENERATOR i-ClK MilO

~m i-READY 'ilffii

i-RESET I\li

I

^{ROY \VA} I

GNO

r-l--,

_OT/A 1 - - - " ^I I

I _WAIT I

m

f-- - - , I I

I ^STATE I _{B086 CPU} I I

r---,

_I

I GENERATOR I I I ^I I

L ___ ...l

^{ALE ClK I} _I

GNO-T-f---:. II I

I I

ADo·AOn ^{A,e-A'9 SHE} rOO~ ^{f-~ LATCH. 20R3}

e

^{ADDR I}

I I I

I I

r;!,;---:l

^I _I

I L _ 0 1 ; - - - - ' I L--111 II I

~ TRANSCEIVER I DATA L

I (21

'1_

1111 111 If: 11

I I SHE

L ___ f

OPTIONAL CSOH CSOL WE 00 CE DE CS ROWR

FOR INCREASED

DATA BUS DRIVE 2142 RAM (4) 27162 PROM (21 MC5-80 PERIPHERAL (21 121

1Kx8 I ^{lKxB 2KIICB I 2Kx8}

231455-5

Figure 4a. Minimum Mode 8086 Typical Configuration

D

Vee

lUi

~CLK

^I

I2MA MN/MX -GNO ClK IiiRiiC

CLOCK SO SO iiWTC

GENERA.TOA

~,m i-READY S; S; AMWC f---N,C,

G

i-RESET 52 52 ⁸²⁸⁸ -_IOAC

I

^{ROY , - -DEN} C~~~R IOWC

NO

r-l--,

⁸⁰⁸⁸ CPU

^-

^{OT/A AiOWC _NC,} ALE iNTi

I WAIT I

I STATE I

=

^{- N e}

r---:l

I GENERATOR I

L ___ ...l

CLK I

GND II I

ADo-AD,S lATCH I

A,e-A'9 ~OOR/OA~ (20R3) ^~DDR

~~

IIIfE ~

-

~

^{OIR II '}

TRANSCEIVER DATA

(21

mo11 _{l1lT II}

~ ^SHE

CSOH CSOl WE 00 CE OE CS JIljWII

2142 RAM (4) 2716·2 PROM (2) MCS·80 PERIPHERAL (21 121

1Kx8 I 1KIC8 2KlC8 1 2KxB

231455-6

Figure 4b. Maximum Mode 8086 Typical Configuration