A continuous-time multi-stage noise-shaping delta-sigma modulator for next generation wireless applications

A Continuous-Time Multi-Stage Noise-Shaping

Delta-Sigma Modulator for Next Generation AROHIVE

Wireless Applications

MA

by

Do Yeon Yoon

B.S., Electrical Engineering

Korea Advanced Institute of Science and Technology (2010)

S.M., Electrical Engineering and Computer Science

Massachusetts Institute of Technology (2012)

Submitted to the Department of Electrical Engineering and Computer

Science

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy in Electrical Engineering and Computer Science

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

June 2015

Massachusetts Institute of Technology 2015. All rights reserved.

Signature redacted

Author ...

of Electrial-

Engneerin

...

Department of Electrical Engineering and Computer Science

Certified by...

Signature redacted

May 14, 2015

Hae-Seung Lee

ATSP Professor of Electrical Engineering

Accepted by

...

* , . .

Thesis Supervisor

Signature redacted

...

/

(f( Leslie A. Kolodziejski

Professor

Chair, Department Committee on Graduate Students

SSACHUSETTS NSTI~ TTE

OF fECHNOLOLGY

JUL

0

7

2015

A Continuous-Time Multi-Stage Noise-Shaping Delta-Sigma

Modulator for Next Generation Wireless Applications

by

Do Yeon Yoon

Submitted to the Department of Electrical Engineering and Computer Science on May 14, 2015, in partial fulfillment of the

requirements for the degree of

Doctor of Philosophy in Electrical Engineering and Computer Science

Abstract

A continuous-time (CT) delta-sigma (AE) modulator for modern wireless

commu-nication applications is investigated in this thesis. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function (NTF). In order to increase the effective order of the NTF, a 2-loop sturdy multi-stage noise-shaping (SMASH) architecture is utilized. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT)

SMASH architecture due to the inherent sampling frequency limitation of the DT

implementation. Furthermore, the proposed CT SMASH architecture provides a bet-ter quantization noise suppression capability than the DT SMASH architecture by more completely canceling the quantization noise from the first loop. The CT SMASH architecture is implemented with several circuit techniques suitable for high operation speed. These circuit techniques allow the proposed CT AE modulator to achieve wide bandwidth, high resolution, and low power consumption for modern wireless commu-nication applications. As a result, the prototype fabricated in 28nm CMOS achieves DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier FOM of 172.9dB over a 50MHz bandwidth at a 1.8GHz sampling frequency.

Thesis Supervisor: Hae-Seung Lee

Acknowledgments

During my Ph.D. journey at MIT, I have met many people who have helped and supported me.

First and foremost, I would like to express my sincere gratitude to my advisor, Professor Hae-Seung Lee. I have always been inspired by his extensive knowledge and creative intuition in analog circuit design. His technical guidance and constant encouragement have allowed me to complete my research successfully. Moreover, I have been able to learn his teaching, writing, and presentation skills. It has been an enormous privilege to work with him.

I would like to thank Stacy Ho at MediaTek for his unwavering support and caring

guidance. He has been always willing to discuss all my complicated technical issues. His great insight from his profound experience in delta-sigma converters showed me the right directions, whenever I faced difficult technical problems. He also provided me the fantastic working environment, resources, and many opportunities at MediaTek.

I would also like to thank Professor Ruonan Han for being on my thesis committee. He has given me many priceless suggestions to improve my thesis.

I would like to thank Michael Ashburn, Chi-Lun Lo, Steven Chiu, Yun-Shiang Shu, CC Hsiao, Joshua Bamford, Vinh Thai, Pier Bove and Zchicheng Wei at MediaTek

for their technical support. Since they are the real experts in circuit design, layout, and measurement, I have been able to learn invaluable skills from them.

I would like to thank Jeffrey Gealow and Paul Ferguson at ADI, who initially

suggested the interesting research topic I have worked on. They helped me to under-stand delta-sigma converters. I am thankful to Jialin Zhao and Jose Silva at ADI for valuable discussions.

I would like to thank Sabino Pietrangelo for his tremendous support. I have relied

on his support and encouragement during my entire Ph.D. life. He has been not only a great colleague but also a fantastic teacher who has taught me writing, presentation and even exercise skills.

research group. Every time I had problems in any topics, they patiently answered my questions with their deep knowledge and experience.

I would also like to thank all the other members of the Lee and Sodini research

groups for the best office environment ever and the many memorable social events. I will not forget the enjoyable memories with senior members (Kailiang Chen, David He, Jack Chu, Mariana Markova, Albert Chang, Khoa Nguyen, and Daniel Kumar) and junior members (Xi Yang, Joohyun Seo, Grant Anderson, and Meggie Delano).

Frank He was a great colleague at MediaTek. Technical discussion with him was truly helpful. Also, we had lots of fun together at MediaTek.

Last but not least, I would like to thank my family. My father and mother have always given me unconditional love, which I have completely depended on during my entire time at MIT. I would also like to thank my sister for her full support. I could never have completed my journey this far without them.

Contents

1 Introduction

1.1 M otivation . . . .

1.2 Thesis Organization. . . . .

2 AE Modulator Overview

2.1 Quantization Noise Suppression . . . . 2.1.1 Quantization Noise . . . .

2.1.2 Oversam pling . . . .

2.1.3 Noise Shaping . . . .

2.2 DT A E ADC . . . .

2.3 CT A E ADC . . . .

2.3.1 Comparison between DT and CT AE Modulators

2.3.2 CT AE Modulator Issues . . . .

2.3.3 Practical Synthesis of a CT AE Modulator with High

Frequency . . . . 2.3.4 Overall Design Process . . . .

2.4 Strategies for Quantization Noise Suppression . . . .

15 15 20 21 21 22 23 25 . . . . 27 . . . . 28 . . . . 29 . . . . 30 Sampling . . . . 34 . . . . 38 . . . . 41

3 Multi-Stage Noise-Shaping AE Modulator

3.1 Original MASH Architecture . . . .

3.2 DT Sturdy-MASH (SMASH) Architecture . . . .

4 CT 3-1 SMASH AE Modulator

45 45

51

4.1 Advantages of a CT 3-1 SMASH AE Modulator . . . . 54

4.2 Two Main Challenges of CT 3-1 SMASH AE Modulator Implementation 61 4.2.1 Analog Delay . . . . 61

4.2.2 Feedforward Path in the 2nd-loop . . . . 65

5 Prototype Implementation

69

5.1 Circuit Implementation . . . . 69

5.1.1 CT 3-1 SMASH AE Modulator . . . . 69

5.1.2 A m plifiers . . . . 75

5.1.3 Quantizer to DAC Path . . . . 85

5.1.4 DACs and Their Calibration . . . . 87

5.2 L ayout . . . .

91

6 Prototype Characterization

99

6.1 Test Environment . . . . 100

6.2 SNR, SNDR, and SFDR . . . . 103

6.3 Intermodulation Distortion . . . . 106

6.4 Signal Transfer Function . . . . 106

6.5 Power Consumption . . . . 107

6.6 Com parison . . . . 108

7 Conclusions

111

7.1 Thesis Contribution. . . . . 111

List of Figures

1-1 _{Signal bandwidth and DR requirements for ADCs in wireless applications 16}

1-2 LTE-A cellular base-station receiver block diagram . . . . 17

1-3 Signal bandwidths and DRs of recent ADCs . . . . 18

1-4 Signal bandwidths and FOMs of recent ADCs . . . . 18

2-1 Analog-to-digital conversion . . . . 21

2-2 _{2-bit quantizer characteristics: (a) transfer curve, (b) quantizer error,} (c) probability density function . . . . 22

2-3 Power spectral density . . . . 23

2-4 Attenuated in-band noise . . . . 24

2-5 Linear model of a DT AE modulator . . . . 25

2-6 Shaped in-band quantization noise . . . . 27

2-7 Block diagram of a DT AE ADC . . . . 28

2-8 Block diagram of a CT AE ADC . . . . 28

2-9 CT AE modulator with a DAC error . . . . 30

2-10 Quantizer to DAC path . . . . 31

2-11 DAC output with jitter . . . . 33

2-12 Open-loop block diagrams: (a) DT AE modulator, (b) CT AE modulator 34 2-13 Common DAC waveforms and their Laplace transforms: (a) NRZ, (b) return-to-zero (RZ), (c) Exponential . . . . 36

2-14 Impulse response comparison: (a) DT loop filter and CT path, (b) matched impulse response . . . . 37

2-16 Outputs in Figure 2-15: (a) y[n] and [ho hi h2 h3] C, (b) outputs from

all paths . . . . 38

2-17 Overall design process . . . . 39

2-18 Feedback structure with an opamp and impedance components: (a) schematic, (b) block diagram . . . . 40

3-1 A general MASH architecture . . . . 45

3-2 A 2-loop MASH architecture . . . . 47

3-3 1'-loop of a CT 3-1 MASH AE modulator . . . . 48

3-4 SQNR results based on different DC gain values . . . . 49

3-5 Three feedforward coefficient variation effects with a -2dBFS input . . 50

3-6 A DT SMASH architecture . . . . 51

4-1 A CT SMASH architecture . . . . 53

4-2 E1 path . . . . 54

4-3 Further reduction of E₂ by gain and attenuation blocks . . . . 56

4-4 Block diagrams: (a) CT 4th-order single-loop AE modulator, (b) CT 3-1 SMASH AE modulator . . . . 57

4-5 STFs from the behavioral simulation . . . . 59

4-6 Quantizer input spectra from the behavioral simulation . . . . 60

4-7 Quantizer input transient wave forms from the behavioral simulation 60 4-8 Block diagram of the CT 3-1 SMASH AE modulator . . . . 62

4-9 Analog delay implementation . . . . 63

4-10 SQNR results based on different LPF time constants with different input frequencies . . . . 64

4-11 STF variation based on different LPF time constant values . . . . 65

4-12 2"d-loop implementation . . . . 65

4-13 2ndloop implementation: (a) with a feedforward path, (b) without a feedforward path . . . . 66

4-14 SQNR results with and without a feedforward path at different input frequencies . . . . 67

5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25

DAC1 driver for an NMOS element. Die photograph of the entire chip Die photograph of the analog core Overall floor plan . . . . Layout of the modulator... Layout of two loop filters . . . . Layout of Quantizer 1 . . . .

Layout of DAC . . . . Layout of DAC, NMOS element . . Layout of DAC1 drivers and DAC1

5-26 Layout of NMOS mirrors in the curr

Overall schem atic . . . .

Overall timing diagram . . . . Additional DACs for the zero-order path . . . .

All feedforward paths using outer-feedback DACs . . .

1s-loop NTF change due to 30% Rzi variation . . . .

Two-stage opamp without compensation: (a) topology, response ... ...

M C topology . . . .

Two cases of the FFC topology . . . .

FFC topologies: (a) option 1, (b) option 2 . . . .

FFMC-PZ: (a) topology, (b) frequency response . . . .

Two-stage amplifier in the lIt-loop . . . .

OTA in the 2nd-loop . . . .

Quantizer 1 to DAC2 path . . . .

Comparator schematic . . . .

DAC unit-cell schematics: (a) DAC, and DAC1 ', (b) D

DAC1 NMOS element connecting to a current copier refe

frequency

AC2 and DAC3

rence cell and

69 71 72 72 74 76 77 79 80 81 84 85 85 86 88 . . . . 89 . . . . 92 . . . . 92 . . . . 93 . . . . 93 . . . . 94 . . . . 95 . . . . 95 . . . . 96 . . . . 97

ent copier circuit . . . . 97

6-1 Measurement setup . . . .

(b)

6-2 PCB for the measurement . . . 102 6-3 Test environment . . . . 102 6-4 Measured 16384-point FFT spectrum with a -3.1dBFS input signal at

5.93M H z . . . 103

6-5 Measured SNR/SNDR based on different input amplitudes . . . 104 6-6 Measured SNDR results at 30, 40 and 50MHz . . . 104 6-7 Measured two tone test results with -8.4dBFS inputs: (a) at 21 and

25MHz, (b) at 13.5 and 15.5MHz . . . . 105 6-8 M easured STF . . . . 106 6-9 _{Power breakdown . . . . 107}

List of Tables

5.1 Component parameters . . . . 74

6.1 Package information . . . . 100 6.2 Comparison with sate-of-the-art>50MHz CT AE modulators . . . . 108

Chapter 1

Introduction

The majority of electronic systems interface with the physical world in the analog domain. Since many systems process signals in the digital domain, it is necessary to convert from the analog to the digital domain. Therefore, an analog-to-digital converter (ADC) is one of the most vital parts in most electronic systems. Wireless communication applications, in particular, need fast and accurate ADCs, because the data frequencies keep increasing with the progress in communication technology.

Among many types of ADCs, the popularity of continuous-time (CT) delta-sigma

(AE) modulators for wireless communication applications has increased in recent

years [1-12]. Since the first idea of AE operation was presented [13] and adapted to an actual ADC

[14],

many architectures and techniques for CT AE modulators have been investigated in order to improve the signal bandwidth with high resolution and low power consumption. However, they have not been able to achieve performance metrics for next generation wireless applications. Therefore, this thesis presents an architecture and several techniques for CT AE modulator design which help to achieve high resolution and signal bandwidth for modern wireless applications.

1.1

Motivation

Wireless communication is a rapidly advancing field and new wireless applications are continuously being developed.

DR(bit)

14 GSM New

Wireless

12 CDMA 2000 1x CDMA 2000 3x 4G LTE Application

TD-SCDMA HSDPA 10 Bluetooth WCDMA WLAN 8 6 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 11 50 BW(MHz)

Figure 1-1: Signal bandwidth and DR requirements for ADCs in wireless applications

Figure 1-1 shows the signal bandwidth (BW) and dynamic range (DR) require-ments of ADCs for wireless applications [15]. As wireless applications have progressed, the required specifications of ADCs have also become more demanding. New applica-tions, such as the Long Term Evolution Advanced (LTE-A) communication standard, demand signal bandwidth and resolution over 50MHz and 14-bit, respectively.

Figure 1-2 shows a cellular base-station receiver block diagram for the LTE-A standard at a radio-frequency (RF) bandwidth of 100MHz. At the front of the

re-ceiver, the low noise amplifier (LNA) amplifies the RF signal. This amplified signal

is down-converted by mixers. The base-band signals are further amplified by variable gain amplifiers (VGAs), and then filtered by low-pass filters (LPFs). Finally, signals are sampled by ADCs. For a higher system-level integration, the power consump-tion of ADCs must be limited. The requirement of power consumpconsump-tion is important for longer battery lifetimes in cellular mobile receivers as well. In order to meet these speed, resolution, and power requirements for modern wireless communication applications, an ADC architecture selection is critically important.

Figure 1-3 shows the reported DRs and signal bandwidths of ADCs at the Inter-national Solid-State Circuits Conference and Symposium on VLSI circuits from 1997

RF BW:

10MHz

LNA

VGA

BW:

50MHz

ADC1

D11

PLL1

PLL2

90*

900

X,..gDQ

,.

ADCQ

Figure 1-2: LTE-A cellular base-station receiver block diagram

to 2014 [16]. Figure 1-3 shows that AE modulators or pipeline ADCs achieve high DRs over 70dB. For DRs over 80dB, AE modulator based designs are dominant. CT architectures are typically used for signal bandwidths over 10MHz.

In terms of power consumption, CT AE modulators are advantageous in wide signal bandwidth applications. When comparing designs, a Figure-of-Merit (FOM) is a good criterion, since it can account for speed, resolution, and power. A common FOM used in ADC design is calculated as shown in Equation 1.1, where P is power and BW is signal bandwidth.

FOM

=

DR+

₁₀₁₀

g(

BW)

P

(1.1)

ADCs with higher FOMs are more power-efficient. Figure 1-4 shows the reported FOMs of ADCs. With signal bandwidths over 10MHz, CT AE modulators have relatively high FOMs. Moreover, a CT AE modulator has a simple resistive input, unlike SAR or pipeline ADCs that require power-hungry input buffers to drive their large switched input capacitors. Also, the anti-aliasing function inherent in a CT

AE modulator reduces the anti-alias filter (AAF) requirements. Therefore, a CT AE

120 110 100 90 ₀ C i S S 80 70 60 50 * U U 40 30 20 IE+03 IE+04 S .U a C 1E+C U * *V 13 a' m * * 0 A A&0oh A& A

5 1E+06 1E+A 1E+0 M E0 'E1A

: A *Ax A A* 0 A* A 0,> A 0EA A+ ++ t +~ + #+ +0 * + + + x1+

5 IE406 IE.07 IE.08 1E+09 IE+10

Signal Bandwidth (Hz)

E This Work * CT Delta-Sigma * DT Delta-Sigma A Pipeline SAR + Flash * Folding o Two-step o Others IE+11

Figure 1-3: Signal bandwidths and DRs of recent ADCs

0 a I A

~

A xA A *P A: q AAL 4 A &A e~~~ EA .. A P 4'" a S A 0A AOA A +0A A A A %U 0 a A U A a 0 *t- .4-o S A Ai + A A EThis Work * CT Delta-Sigma * DT Delta-Sigma A Pipeline SAR + Flash * Folding 0 Two-step * Others 100

IE+03 IE+04 IE+05 IE+06 IE+07 IE+0B 1E+09

Signal Bandwidth (Hz)

IE+10 IE+11

Figure 1-4: Signal bandwidths and FOMs of recent ADCs C

E

aV

C

190 180 ~0 S S 4-u S E 0 0 S 0 0 gO 170 160 0150 * 0140 U. 130 x C -0 a 120 110 ++ + +

i

+

wide signal bandwidth, high resolution and low power consumption.

Unfortunately, the design of CT AE modulators is significantly more complex than discrete-time (DT) AE modulators. Since the implementation methodologies of AE modulators began with DT, many DT implementation schemes have been thoroughly examined. On the other hand, the implementation of CT AE modulators is not straightforward, since it is based on the conversion from DT AE modulators. Also, all distortion sources of CT AE modulators are different from those of DT

AE modulators. Thus, new approaches to implement CT AE modulators for high

resolution and wide bandwidth are an active area of research.

Several state-of-the-art CT AE modulators reported recently achieved signal band-widths 50MHz or higher, which are required in next generation wireless communica-tion standards [3,6,7,11,17]. However, the resolucommunica-tion and power consumpcommunica-tion of these designs can be improved.

For these reasons, this thesis presents a new CT AE modulator architecture to achieve high resolution and wide bandwidth, while consuming low power [12]. This work seeks to achieve 50MHz signal bandwidth, DR greater than 84dB, and power consumption below 100mW. Along with this architecture, several practical techniques are proposed to achieve these target performance metrics. The fundamental idea is to implement a CT multi-stage noise-shaping (MASH) AE modulator consisting of 3 rd

and 1st-order loop filters based on a Sturdy-MASH (SMASH) architecture previously reported in a DT AE modulator

[181.

This architecture achieves the similar noise suppression to the ideal MASH architecture without requiring digital filters for quan-tization noise cancellation. Moreover, several circuit techniques in this thesis mitigate speed constraints and help to achieve wide signal bandwidth and high resolution while maintaining low power consumption.

There are three distinct objectives for this thesis. First, this thesis introduces the advantages of the proposed CT 3-1 SMASH AE modulator. In the proposed CT

3-1 SMASH AE modulator, benefits from the previous DT SMASH AE modulator

are enhanced. Furthermore, the proposed AE modulator has improved performance compared to a CT single-loop AE modulator with the same noise-shaping capability.

Second, this work presents the main challenges and their solutions of the proposed

CT 3-1 SMASH AE modulator in the architecture-level. Compared to the previous

DT SMASH AE modulator, there are several differences in the CT SMASH imple-mentation. These differences bring about new unique design challenges. To overcome these issues, proper architecture-level solutions are proposed. Third, this thesis shows several circuit-level techniques, which mitigate design complexity and improve per-formance. After solving key challenges in the architecture-level, there are still several practical issues in the level implementation. This thesis will show the circuit-level techniques employed to relax the requirements and improve the performance of each essential block in the modulator.

1.2

Thesis Organization

A CT AE modulator with a SMASH architecture for next generation wireless

appli-cations is proposed in this thesis. The thesis is organized as follows:

Chapter 2 describes the fundamentals of AE modulators. CT AE modulators are studied primarily to help motivate the remainder of the thesis. Several issues arise when a DT AE modulator is converted to a CT AE modulator, which are described in detail.

Chapter 3 provides an explanation of MASH architectures. The original MASH and SMASH architectures are investigated.

Chapter 4 proposes a CT AE modulator based on the SMASH architecture. In this chapter, advantages and challenges of a CT 3-1 SMASH AE modulator are presented. Chapter 5 describes the actual implementation of the proposed CT 3-1 SMASH

AE modulator. Details from the circuit-level design are presented. Layouts of the

core blocks are shown as well.

Chapter 6 shows the measurement results from the prototype integrated circuit

of the CT 3-1 SMASH AE modulator.

Chapter 2

AE Modulator Overview

This chapter provides fundamental information about AE modulators. First, the main characteristics of AE modulators, which is to suppress quantization noise, are described. Based on these characteristics, the overall structure of a AE modulator is

illustrated with operational descriptions. In addition, differences between DT and CT

AE modulators are discussed. The main advantages and issues of CT AE modulators

are presented to aid in understanding the rest of the thesis.

2.1

Quantization Noise Suppression

This section shows the quantization noise suppression characteristic of a AE

mod-ulator. First, general quantization noise in an ADC is described. The quantization

noise is suppressed by the oversampling and noise shaping characteristics of a AE

modulator. These two characteristics are explained in this section.

X(t)

S/H

--

+

_ yd

f f-fN-bit

AAF

fs

Quantizer

2.1.1

Quantization Noise

Quantization noise is the difference between the analog input value and quantized digital ADC output. Figure 2-1 shows the general conversion process from an analog signal to a digital signal. The process of this conversion is to sample a CT signal using a sample-and-hold (S/H) circuit and then to assign this sampled value to one of the discrete values. This process is commonly referred to as quantization. Before the CT signal is sampled, an AAF is required to prevent high frequency components from folding into the signal bandwidth. This conversion is further explained with a 2-bit quantizer. Y.O e=y-xA

...

....

1...

LSB A 2 Non-overload Input range A A e (a) (b) (c)

Figure 2-2: 2-bit quantizer characteristics: (a) transfer curve, (b) quantizer error, (c) probability density function

The characteristics of a 2-bit quantizer are shown in Figure 2-2. Figure 2-2(a) shows the transfer curve of this quantizer from input to output. The quantizer step size is shown as A. The least significant bit (LSB) is the difference between the two adjacent quantizer levels. These two values are equivalent, and are given by A

= LSB = FS/4, where full-scale (FS) is the maximum input range. With an n-bit

quantizer, in general, the quantizer step size and the LSB are given by A = LSB =

FS/2'. Figure 2-2(b) shows the quantizer error e, which is the difference between the

input and the output of the quantizer. Within the non-overload input range, given

by [-FS/2, FS/2j, e is distributed within the range -A/2, A/2]. In this example, e is

correlated with the input, but under certain circumstances [19-22}, it can be modeled as white noise that is uniformly distributed in the range I-A/2, A/2}, as shown in

SE

()2

12fs,

A2 12fs 2 fs2 fS -fB fB fS I S2

2

2

2

2

Figure 2-3: Power spectral density

noise power a2 can be calculated. Since quantization noise power is also uniformly

distributed in the range [-fs/ 2_{, fs/}2_{] where}

_fs

is the sampling frequency, the power spectral density of the quantization noise is given by:

2 1 1 A/2 A2

SE e -- e2d __

fs fs[A -A/2 =12fs (2.1) Figure 2-3 shows the power spectral density of the quantization noise, which is constant in the range [-fs/2, fs/2. Total integrated noise power is always A2_/12,

regardless of a sampling frequency. However, within the signal bandwidth, the inte-grated quantization noise power is given by:

PE fB SE(f)df - 2fBA2 (2.2)

_fB 12fs

where fB _{represents the signal bandwidth.}

2.1.2

Oversampling

According to the Nyquist Theorem, the sampling frequency fs must be greater than

twice the signal bandwidth 2fB, generally referred to as the Nyquist rate. Unlike

S E

_I

_M)

Attenuated in-band

quantization noise

(PE)

fB

fsi/2

fs2

/2

f

Figure 2-4: Attenuated in-band noise

ADCs use the sampling frequencies much higher than the Nyquist rate 2fB. The

oversampling ratio (OSR) is defined as fs/2fB. Figure 2-3 and Equation 2.2 show that

the quantization noise power within the signal bandwidth decreases as the sampling

frequency increases for given signal bandwidth. This effect is shown more clearly in

Figure 2-4. Equation 2.2 is rewritten using OSR.

PE =

_ B

2fBA2 __2_

SE(f)df

2_{fs 12OSR}

12fs 120SR

(2.3)

Equation 2.3 shows that the in-band quantization noise power is inversely proportional

to the OSR. Since the fixed quantization noise power o is uniformly distributed in

the range [-fs/2,

fs/2,

the in-band quantization noise is reduced with increasing

sampling frequency. Another advantage of oversampling ADCs is that a high sampling

frequency relaxes the requirements of the AAF in Figure 2-1, since the sharp AAF

at the input of the S/H circuit is not required. These advantages of oversampling

ADCs are obtained by increasing the sampling speed, potentially at the cost of higher

overall power consumption of the ADCs.

Loop Filter Quantizer _{Loop Filter}

U + + H(z) V U + + H(z) + V

+

E _E

Figure 2-5: Linear model of a DT AE modulator

2.1.3

Noise Shaping

With a sampling frequency higher than the Nyquist rate, the oversampling charac-teristic of a AE modulator reduces the in-band quantization noise power. A AE modulator has another characteristic, known as noise shaping, that suppresses the in-band quantization noise power further. This noise shaping characteristic comes from the feedback architecture of a AE modulator and proper loop filter design. The main idea of noise shaping is that the loop filter in a AE modulator pushes in-band noise to out-of-band frequencies.

Figure 2-5 shows a general block diagram of the DT AE modulator. It consists

of a feedback system with a loop filter H(z) and a quantizer. U and V represent the input and output of the AE modulator, respectively. The quantizer block can

be modeled as an addition of quantization noise, E, in a linear system model. The output of this linear feedback model in Figure 2-5 is given by:

~

H(z) 1

V =U-Hz + E- 1(2.4)

1+H(z) 1+H(z)

From Equation 2.4, the signal transfer function (STF) and the noise transfer function

(NTF) are defined:

H(z) 1

STF = _{1+ H(z)} NTF =

1(2.5)

I1+ H(z)

Within the signal bandwidth, if the loop filter H(z) has large gain, then STF and

NTF become nearly 1 and 0, respectively, based on Equation 2.5. This means that a AE modulator passes its input signal and blocks the quantization noise at its output.

gain near DC. For band-pass AE modulators, resonators, which have large gain at their given center frequency, are used in general.

To explore the noise suppression effect from the NTF further, the general Lth-order

NTF is given by:

NTF = (1 - z-1)L (2.6)

To calculate the in-band quantization noise power suppressed by this NTF, the mag-nitude of the NTF is calculated.

INTF(ej")

= 1 - -, = 1- cos(Q)

+

j

sin()

2

L

= [2-2 cos()]L 2sin( Q)] (2.7)

where normalized Q is defined as 0=27rf/fs. In a AE modulator, the quantization noise is reduced by a high sampling frequency, and then suppressed further by the

NTF. The final in-band quantization noise power at the output of a AE modulator

is the integration of the shaped quantization noise power spectral density. PQ 1

JO

,2NTF (e")

|

2_{df =}

2

J2

sin( )]

df (2.8)

where normalized QB is defined as QB=r/OSR. Due to the oversampling character-istic, generally, ir/OSR is very small. Then, within the range [0, ir/OSR], the sine term is simplified as:

2 - sin -₂

2

= Q (2.9)

2

The final in-band noise power shaped by the given NTF is represented as:

p

A2 fr/OSR AA 2 12L

127r Jo

12

(2L

+

1)OSR2L+1

the noise shaping characteristic further suppresses quantization noise. As shown in

Equation 2.10, the quantization noise power is reduced by the OSR at a rate of 6 L-3

dB/octave.

In summary, the in-band quantization noise is suppressed with a high sampling

frequency, because the fixed quantization noise is distributed uniformly over the range

[-fs/2,

fs/

2

_{]. This in-band quantization noise is reduced further by the feedback}

system with the NTF. This final shaped quantization noise is illustrated in Figure

2-6.

SE

_M

(Te 2

NTF12

B

s

Shaped in-band

quantization noise

_(PQ)

Figure 2-6: Shaped in-band quantization noise

2.2

DT

AE

ADC

Figure 2-7 shows the overall block diagram of a DT AE ADC. There are an AAF,

a DT AE modulator, and a decimation filter. Unlike a CT AE modulator, the

CT input signal x(t) is sampled at the front of the AE modulator to process the

received signal in the discrete-time domain. Therefore, in order to avoid aliasing

when the signal is sampled, an AAF is required before the DT AE modulator. The

+ _{Loop Filter} Quantizer x(t) S/H + H(z) N-bit + Yd(n) t t: AAF fs E Decimation DT AX Modulator E Filter

Figure 2-7: Block diagram of a DT AE ADC

quantization noise E is suppressed by the NTF from the DT loop filter H(z) and the feedback loop. The feedback path typically consists of switched-capacitor (SC) digital-to-analog converters (DACs). The DT loop filter is also a SC type. Since the output of the AE modulator is generated at a high sampling frequency, the output data frequency of the AE modulator must be reduced to the Nyquist rate for use in subsequent signal processing blocks. Therefore, a decimation filter is required at the output of the DT AE modulator, in order to realize an overall DT AE ADC.

2.3

CT

AE

ADC

Loop Filter * Quantizer

x(t)

+

H(s)

S/Hit

+ OSR J- yd(n)

: :t t

fs

E

Decimation

CT Al Modulator : Filter

Figure 2-8: Block diagram of a CT AE ADC

The overall block diagram of a CT AE ADC is shown in Figure 2-8. One of main characteristics of a CT AE ADC is that the CT input signal x(t) is directly applied to the input of the CT AE modulator. Thus, the loop filter in a CT AE modulator employs CT components such as RC and Gm-C integrators. RC integrators are employed for larger signal swing and better linearity, whereas Gm-C integrators are

employed for higher operation speed [23, 24J. For the feedback implementation, in

general, either SC DACs [25-28] or current-steering DACs [1,3,6-8,11,12,29-35] are

employed. Unlike the DT AE ADC, the CT signal is sampled at the quantizer. The

CT loop filter provides an inherent AAF [36]. Therefore, the AAF requirements can

be relaxed in a CT AE ADC. However, following the CT AE modulator, a decimation filter is still required.

2.3.1

Comparison between DT and CT AE Modulators

The modulators in AE ADCs can be implemented in either DT or CT. In general, DT

AE modulators consisting of SC circuits more readily achieve higher accuracy than CT AE modulators. This is because the accuracy of the DT AE modulator relies on

precise capacitor matching. Also, DT AE modulators are robust to process variation for the same reason. _{However, SC circuits limit the operation speed of DT AE} modulators, because operational amplifiers (opamps) for SCs circuits need to settle within each half-clock cycle. Another significant drawback of DT AE modulators is the more stringent AAF requirement at the input.

The loop filters of the CT AE modulators, however, do not use SC circuits. Thus, the opamps require much lower gain-bandwidth, therefore easing the design requirements of the opamp. Since there is no sampling process within the filters, the constraint of maximum sampling frequency depends mainly on the regeneration time of the quantizer and the update rate of the DAC [37]. Thus, it is possible for CT AE modulators to operate at higher sampling frequencies and achieve wider bandwidths compared to DT AE modulators.

Modern wireless applications demand wide bandwidths 50MHz or higher. With-out increasing a sampling frequency, it is difficult to simultaneously achieve high resolution and wide bandwidth, due to a lower OSR. Therefore, in order to achieve both wide bandwidth and high resolution, it is necessary for the AE modulator to operate at high sampling frequencies over 1GHz. In order for opamps to fully settle

with SC circuits, the unity gain-bandwidth (UGBW) of the opamp in a DT AE

it is not power-efficient for DT AE modulators to function at sampling frequencies over 1GHz. On the contrary, the UGBW of opamps in active RC integrators that

CT AE modulators use can be lower than about four times the sampling

frequen-cies, depending on the chosen scaling coefficient [39]. Moreover, due to their inherent AAFs, CT AE modulators can save additional power and circuit complexity. For these reasons, CT AE modulators are appropriate to meet the demands of modern wireless applications.

2.3.2

CT AE Modulator Issues

Quantizer

U

HLF(S)

-dl

CLK

+DAC(s)

Z d

EDAC

DAC Driver

Figure 2-9: CT AE modulator with a DAC error

Despite the several advantages of CT AE modulators, such as low power con-sumption and high speed operation, there are three main issues, especially when high sampling frequencies are exploited for wide bandwidths: (1) excess loop delay (ELD), (2) non-linearity of multi-bit DACs, and (3) DAC clock jitter. Figure 2-9 shows a CT

AE modulator with a DAC error. The error EDAC added at the output of the DAC is the most important error because it is not shaped by the loop filter. On the other hand, the error occurring between the loop filter and the quantizer is suppressed by

the loop filter similarly to quantization noise.

The ELD is due to the finite response times of the quantizer and the DAC circuits in the modulator

[40].

In a CT implementation, since the quantizer cannot generate its output instantly, the quantizer is given a delay for regeneration. Thus, at least one latch is located between the quantizer and DAC. In Figure 2-9, two latches with T dl

and Td2 are for the quantizer and DAC driver, respectively. The quantizer latch is triggered after the comparators make the decision. The DAC cannot also generate its output immediately, due to DAC driver propagation delay, DAC switch delays, and the DAC settling time. Moreover, the delays that occur from all integrators due to the finite UGBWs add ELDs [41], especially at high sampling frequencies. To compensate for ELDs, several methods have been proposed [42]. Among these methods, the most popular technique is to allow a certain delay between the quantizer to the DAC and add an additional fast feedback path from the output to the input of the quantizer [43]

to compensate the ELDs.

f

-Tdl

-Td2

DAC(s)

At2

Ata"

Output

0 ''Time

Comparator Td.1 Td2

CLK Quantizer DAC Driver

EDGE Latch CLK Latch CLK

EDGE _EDGE

At1 : Regeneration Time

A2 _{: Latch Propagation Delay}

ta: Latch Propagation Delay + DAC Switch Delay

Figure 2-10:

Quantizer

to DAC path

Figure 2-10 shows ELDs from the quantizer to the DAC, when there is no cir-cuitry between these two blocks. After the comparator is triggered, the quantizer

latch and the DAC driver are triggered at Td, and Td2, respectively. At,, At2, and At3 are the comparator regeneration time, quantizer latch propagation delay and the

sum of DAC driver latch propagation and DAC switch delays, respectively. A suffi-ciently large Tdl is necessary in order to allow for the variation in regeneration time At,, and alleviate quantizer metastability concerns [441. Also, Td2 must occur after Tdl+At2. At Td2+At3, the loop filter receives the DAC output. In general, from the

system-level design, the DAC output timing is given and the ELD budget is set based on this timing. At high sampling frequencies, At1 , At2, and At3 are not negligible. As a result, the sum of At,, At2, and At3 may limit the sampling frequency.

More-over, if any additional circuits such as dynamic element matching (DEM) circuits are added between the quantizer and the DAC, the timing budget becomes even tighter. Therefore, proper timing allocation is crucial at high sampling frequencies.

In recent state-of-the-art CT AE modulators, multi-bit quantizers have been used to further reduce quantization noise, to improve the modulator stability, and to reduce the effect of timing jitter. Along with additional power consumption from more com-parators, a multi-bit quantizer requires a multi-bit DAC. A multi-bit DAC consists of several unit cells, based on the number of bits. Ideally, the current value from each unit cell should be exactly the same. However, due to mismatches, each unit cell has a different current value. The output of a multi-bit DAC therefore creates non-linear errors. This is modeled as EDAC in Figure 2-9. Unlike the quantization and loop filter errors, EDAC is not shaped by the loop filter, because this error is added to the loop at the input. As a result, EDAC is seen at the output without suppression by the loop filter. Therefore, it is often necessary to reduce this error with additional calibration or mismatch shaping methods. Many techniques have been proposed to calibrate the non-linearity from multi-bit DACs such as analog calibration

[45],

digital correc-tion [4,31,46], and dynamic element matching (DEM) [47] [48]. DAC non-linearity is a common problem for all AE modulators, but it is much more severe in CT AE modulators with current-steering DACs, since the matching in current-steering DACs is worse than in SC DT DACs.

de-Ideal NRZ

DAC Output

DAC Output

with Jitter

:Error from SJifter n (n+1) (n+2) (n+3) (n+4) *Ts OFm * S STime

Figure 2-11: DAC output with jitter

grades the resolution [491. This effect is shown in Figure 2-11. The ideal

non-return-to-zero (NRZ) DAC output is the step waveform with the identical sampling period

Ts. However, with the DAC clock jitter, each actual sampling period is not

identi-cal. Then, the amount of charge transferred to the loop filter becomes inaccurate as

shown in Figure 2-11. Since this is equivalent to a DAC error, it is not suppressed by

the loop filter. The similar clock jitter error occurs at the quantizer as well, but is

reduced by the loop filter because it is considered quantization noise. The clock jitter

error from the DAC can be attenuated by using a multi-bit quantizer and DAC, since

the amount of the error introduced by jitter between each level is reduced. However,

this solution suffers from the same multi-bit DAC linearity issues. It is possible to use

a SC topology for DACs in CT AE modulators to reduce the jitter error, since these DACs move stored charge on the capacitors into the loop filter within the sampling time and this amount of charge is barely affected by the DAC clock jitter. However, at high sampling frequencies, a SC DAC topology presents the same disadvantage as the DT AE modulator due to the opamp settling requirement.

2.3.3

Practical Synthesis of a CT AE Modulator with High

Sampling Frequency

The synthesis methodology for DT AE modulators has been well investigated [37,

50, 511. The main part is the implementation of a loop filter. It is not different

from designing an active filter by using SC circuits in the z-domain to implement a target NTF. There are several convenient design tools such as the AE toolbox for MATLAB [51] in order to obtain coefficients for the target active filter.

On the other hand, the synthesis of a CT AE modulator is more complicated. This is mainly because the CT loop filter can only handle a CT signal, while the target

NTF is represented by a z-transform in which only a DT signal can be represented.

Therefore, it is important to find the CT loop filter equivalent to the DT loop filter which can implement the target NTF.

y[n]

H(z)

xDT[n]

(a)

YC (t) XCT )

y[n]

-

DAC

H(s)

-

W' xc[n]

(b)

Figure 2-12: Open-loop block diagrams: (a) DT AE modulator, (b) CT AE modu-lator

Figure 2-12 shows the simplified open-loop block diagrams of DT and CT AE modulators from the output to the input of the quantizer. In Figure 2-12(a), the quantizer output y[n] is applied to the DT loop filter H(z). Then the DT loop filter

produces the quantizer input XDT[n]. In Figure 2-12(b), y[n] is applied to DAC and

CT loop filter output is xCT (t) which is sampled to become the DT quantizer input

X, [n]. The CT AE modulator can act as the DT AE modulator, if both quantizer

inputs in DT and CT AE modulators are equal as follows:

XDT[n] = X,,(t)It=nTS

(2.11)

If the impulse responses of both open-loop blocks in Figure 2-12 are identical at

sampling times, Equation 2.11 is satisfied [52].

Z-1

{H(z)}

= L-{DAC(s)H(s)} t=nT, (2.12)

where DAC(s) is the DAC transfer function. This can be represented in the time

domain [53].

h[n] = [hDAC(t) * h(t)]|t=nTs

j

hDAC(-r)h(t - T)dIt=nTs (2.13)

where h[n], hDAC(t), _{and h(t) are the impulse responses of the DT loop filter, DAC,}

and CT loop filter, respectively. This transformation between DT and CT domains is called the impulse-invariant transformation [54].

Many previous works solved Equation 2.12 or 2.13 to find H(s) [40,47,53]. H(z) is determined from the target NTF. Once DAC(s) is modeled as shown in Figure 2-13, a loop filter transfer function H(s) can be found by solving Equation 2.12 or 2.13 [40]. Figure 2-13 shows three common DAC waveforms [47]. Based on the loop filter topology, coefficients of the loop filter are finally obtained.

This mathematical method to synthesize a CT AE modulator can provide practi-cal loop filter coefficients, if the sampling frequency is low. However, this method does not provide accurate loop filter coefficients for a target NTF at high sampling frequen-cies. The first reason is that it is difficult to model a DAC output waveform precisely at high sampling frequencies. Even with many different waveform models [47], since

Ts becomes smaller, it is difficult to represent the actual DAC waveform with limited

assump-DACNRZ(t)

ot

0

Ts

DACRZ(t) 1+ t 0 t1 t2 Ts DACEXP(t) t 0 t1 t2 Ts

fi,

0

z

sT

DACNRZ 1 : t T

0, otherwise

DACNRZ (s) -e-'TS S

(a)

DACR (t)= 12 t t t2 0, otherwise DA CR (s)= eSt es(t21) S

(b)

0,

_{0: t:5 ti}

DACEXP (t) -1-e t)/, 2 e~(-t2 2 t2 i TS

DACExP (s)2 es!1 (1 es(2t1)) est1 (r r~eS(t2

s(l+sr1)(l+sr2) (1+sr,)(1+sr2)

(c)

Figure 2-13: Common DAC waveforms and their Laplace transforms: (a) NRZ, (b) return-to-zero (RZ), (c) Exponential

tion that active blocks in the loop filter, such as integrators and resonators, are ideal to obtain loop filter coefficients. However, this assumption is no longer true at high sampling frequencies, because any ELDs from active blocks due to finite UGBWs of opamps are not negligible. These effects change pole and zero locations of the NTF from their ideal locations and degrade their noise-shaping ability.

Instead of the previous mathematical method, a simulation-based impulse re-sponse matching method is more practical, especially at high sampling frequencies. The basic concept of the simulation-based impulse response matching method is shown in Figure 2-14(a). By tuning coefficients in the CT loop filter, for a given

DAC, the actual impulse response from the CT path and the ideal impulse response

im-10 Hirl smpulIse response Hkz) of a DT loop filter 3. 2. 1. 0. 1 4L Impulse response

Delay DA

~

)of aCT pats

(a)

Loop Star pulaalhspulaa reaponses (negaWa)

4 -- ----. . .. . . .. . . .- - ---- - . . . ...I- - - --- .. .. . - - --- .. ... . 5 -- -3 .. - --- .. --- ..-- -- --- --- ---.. ....--- -- -- -- .... .... ----- ---.. .. 1 - - --- - (- - -04 1 2 3 4 5 6 7 8 9 (b)

Figure 2-14: Impulse response comparison: (a) DT loop filter and CT path, matched impulse response

pulse responses are well matched at every sampling step, as shown in Figure 2-14(b), this CT path shapes the quantization noise in the same manner as the DT loop filter. This method can be used in MATLAB using Simulink or in Cadence using Verilog-A models, actual transistor-level circuits, or even extracted layout models, which include additional non-idealities. 6[ny L dDelay

DAC (s)

LF (s)

fr-oder Path (s) Path (s) z-rdeT Path (s) Zerorder[

Figure 2-15: Enhanced impulse response matching method for the 3rd-order modula-tor

More accurate loop filter coefficients can be obtained through the enhanced im-pulse response matching method

155].

Figure 2-15 shows the overall flow to use this

Impulse Input i0

(b)

6[n] 1 h[n]

NTF(z)

-]

y[n

6[n] 1

L-hNTF(z)

h3[n]

NTF(z)

h2[n]

NTF(z) -hi[n]

-NTF(z) -ho[n]

method for the 3 d-order modulator. Loop filter coefficients for the target NTF are determined by solving the equation shown below:

h[n]

*

[ lo[n] 1

1

[n]

12[n] 13[n] ] C = 5[n] - h[n] = y[n] (2.14)

where C is the coefficient matrix [CO C1 C2 C3 1T,

h[n]

is the impulse response of

the target NTF, and li[n] is the sampled pulse response from the input of the DAC to the output of the ith-order path in the CT loop filter. Equation 2.14 determines

C by minimizing the rms difference between the right and left side of the equation.

As mentioned before, this method can be easily utilized at the circuit-level with all non-idealities. Since this is a simulation-based method, even with all non-idealities, loop filter coefficients for the desired NTF are easily obtainable without complicated DT to CT conversion. Figure 2-16 shows the examples of the outputs in Figure 2-15.

hi[n] is h[n]*l[n].

-0.21 -0.4 -0.6 -A 0 5 10 15 20 30 35

n

(a)

Figure 2-16: Outputs in Figure 2-15: (a)

all paths 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 .0 C₃ -h₃[n C₂ h2[n] C₁ -h[n] Co -ho[n] -05

n

n

(b)

y[n]

and [ho hi h2 h3] C, (b) outputs from

5 10 15 20 i5i 30 35 40

2.3.4

Overall Design Process

Figure 2-17 shows the overall design process of the CT AE modulator. After the specifications and topologies of the AE modulator are decided, the AE modulator is first implemented in MATLAB using Simulink in order to develop general insight

.... ..----- -...-. -- --- - -.. ---

y[n]

[ho h1 h2 h3]C

U - m

-Behavioral

Simulations

SSimulink

Models

IVerilog-A

Models

Circuit-Level

Simulations

4

CircuiDt

-esign-Post-Layout

Simulations

I

Layout

Debugging

Process

Figure 2-17: Overall design process

Specification

and Topology

Decisions

-into the target AE modulator design. To obtain initial loop filter coefficients, ideal models for the DAC and the loop filter are initially used. Each block can then be successively replaced by a more realistic model and its effects on performance are observed. The impulse response matching method, described in the previous section, is used to update the loop filter coefficients and restore the target NTF, including all non-idealities. As examples of realistic models, the active blocks in the loop filter are modeled.

Zf

in Zf/Z2

A

A(S) Vout P14't.' IZ1+ Zf11Z2 -Vi n _{Z1 -ou} Vout Z1//Zz

Z2

=f

Z+Z1/1 Z2 (a) (b)

Figure 2-18: Feedback structure with an opamp and impedance components: (a) schematic, (b) block diagram

In order to deal with arbitrary opamp models, active blocks are modeled using opamp open-loop transfer functions, A(s). Figure 2-18 shows a general feedback structure with an opamp and arbitrary impedance components connected around it. These impedance components can be resistors, capacitors, or combinations of both.

Z1 and Z2 are driven by the input of a modulator or the opamp of the previous stage.

As shown in Figure 2-18(b), the transfer function is expressed as:

Vo _ -A(s) Zf

n (

+2+A(s) Z15)

z1 Z2

Open-loop active blocks using an operational transconductance amplifier (OTA), such as Gm-C integrators, can also be used in the loop filter. The transfer functions of these blocks are straightforward to derive by using the transfer functions of OTAs

due to the absence of feedback as follows.

= Gm(s)

-

ZLoad (2.16)

where Gm(s) _{and ZLoad are the transfer function and the load impedance of the OTA,}

respectively. Through the impulse response matching method, loop filter coefficients are obtainable for the updated loop filter with active block models including non-idealities.

More realistic behavioral simulations are performed in Cadence using

Verilog-A blocks. Each Verilog-Verilog-A block can be successively replaced by its own circuit-level

block and the performance degradation due to the circuit-level block is verified. Since the performance difference can be observed by replacing each block, the debugging process becomes straightforward. Therefore, it is important to build the entire AE modulator with Verilog-A blocks. Through the impulse response matching method, loop filter coefficients are continuously updated to restore the NTF with non-idealities from the circuit-level blocks. If the restored NTF with updated coefficients is not good enough, redesign of critical circuit-level blocks such as opamps is necessary to improve their performance.

Similarly, circuit-level blocks are then replaced by the extracted circuit models from the layout. With extracted circuit models, loop filter coefficients must again be updated. Because additional non-idealities are added from layout parasitic effects, critical blocks may need to be redesigned iteratively. Once all blocks are replaced by their extracted models from the layout and adequate performance is obtained, the overall design is completed.

2.4

Strategies for Quantization Noise Suppression

To achieve a DR 85dB or higher and to meet block requirements for next generation wireless standards, quantization noise needs to be suppressed aggressively. The quan-tization noise in a AE modulator can be reduced by increasing three main factors:

the OSR, the number of bits of the quantizer (N), and the order of the loop filter

(L). Each method, however, has its own costs.

First, increasing the OSR brings about speed and power issues. Since the tran-sistor fT is limited, simply increasing OSR is not an option in many cases. It also

increases speed requirements and power consumption of every block in a AE mod-ulator, because a higher sampling frequency increases the overall operating speed of a AE modulator. Increasing the number of bits of the quantizer increases its complexity and power consumption. Furthermore, if a multi-bit quantizer is used, non-linearities from multi-bit DACs degrade the linearity of a AE modulator. Since

DAC non-linearities add directly to the input signal, they are not suppressed by the NTF. Increasing the order of the loop filter raises stability and complexity issues. A

modulator with a high-order loop filter becomes conditionally stable with a limited input range [56]. Although less aggressive NTFs provide better stability [57], the in-band quantization noise is higher, and implementation of these NTFs increases circuit complexity because of additional coefficient paths.

Since each method has its own drawbacks, it is important to choose the most effective combination to reduce quantization noise especially at wide signal bandwidth and high DR. To investigate the quantization noise suppression effects of these three methods, the signal-to-quantization-noise ratio (SQNR) is used. When the input of a AE modulator is a sine wave, the SQNR is calculated by comparing the power of the non-overloaded input signal and the in-band quantization noise in Equation 2.10. The non-overloaded input power is given by:

P

(FS/2)

2 (2N-1A) 2