The INRIA ZEP project: NVRAM and Harvesting for Zero Power Computations

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The INRIA ZEP project: NVRAM and Harvesting for Zero Power Computations

Gautier Berthou, Arnaud Carer, Henri-Pierre Charles, Steven Derrien, Kevin Marquet, Ivan Miro-Panades, Davide Pala, Isabelle Puaut, Fabrice Rastello,

Tanguy Risset, et al.

To cite this version:

Gautier Berthou, Arnaud Carer, Henri-Pierre Charles, Steven Derrien, Kevin Marquet, et al.. The INRIA ZEP project: NVRAM and Harvesting for Zero Power Computations. NVMW 2018 - 10th Annual Non-Volatile Memories Workshop, Mar 2018, San Diego, United States. pp.1. �hal-01941766�

G. Berthou, K. Marquet, T. Risset and the ZEP team

Inria, INSA Lyon, CITI Laboratory

The ZEP team: Gautier Berthou, Arnaud Carer, Henri-Pierre Charles, Steven Derrien, Kevin Marquet, Ivan Miro-Panades, Davide Pale, Isabelle Puaut, Fabrice Rastello, Tanguy Risset, Erven Rohou, Guillaume Salagnac, Olivier Sentieys, Bahram Yarahmadi

Kevin.Marquet@insa-lyon.fr

NVMW 2018

The INRIA ZEP project:

NVRAM and Harvesting for Zero Power

Computations

ZEP project: Context and Objectives

Time Vboot

Vdeath

Off time Lifecycles

Vsave

Figure: Examples of batteryless RFID tag and typical On/Off cycles of platforms supplied by energy harvesting, with checkpointing and restoration

Context

I The Internet of Things scenario predicts billions

of communicating objects in a near future.

I Maintenance cost and pollution issues are

major bottleneck for IoT.

I Emerging non-volatile memory (NVRAM)

technologies and harvesting techniques predict new kinds of batteryless embedded sensors.

I Checkpointing [1] of platform state will be a

central technique is these systems.

Challenges

I Provide a new computation model adapted to

NVRAM based micro-systems.

I Master harvesting techniques and energy

control in ultra-low power domain.

I Provide real computer science contributions

(langage, compiler, operating systems, etc...)

I Deliver innovative prototypes and a useful

system-level simulators.

Partners and Methodology

Inria and CEA

I Inria, the French National Institute for computer science and applied mathematics, promotes scientific

excellence for technology transfer and society. Inria is structured in research teams called project-teams.

I CEA, the French Alternative Energies and Atomic Energy Commission is a key player in technological

research for industry. CEA research institutes (List and Leti) are structured in research teams called labs.

I Other institutes such as Insa-Lyon or University of Rennes are involved in Inria project-teams.

I The ZEP project is an Inria Project Lab (IPL), funded by Inria with more than 15 person-years hired

over 4 years, including 3 PhDs. The Insa-Spie IoT Chair is also participating to the research effort of Citi Lab on IoT.

Planning

2017 2018 2019 2020

Task O: IPL management

T0.1: meeting

M0.1 M0.2 M0.3 M0.4 M0.6 M0.7 M0.8 M0.9 M0.10

T0.2: workshop

W0.1 W0.2 W0.2

Task 1: NVRAM architecture

T1.1: ZEP prototype

D1.1 D1.2

T1.2 PhD 1

PhD 1

Task 2: Worst Case Energy Consumption

T2.1: PhD 2 PhD 2 Task 3: NVRAM OS T3.1: Phd 3 PhD 3 Task 4: Demonstrators M4.1 D4.4 T4.2: platform integration D4.3 D4.4 T4.3: demonstrators D4.5 D4.6

Teams and Skills

Rennes Lyon Grenoble Inria Pacap Inria Cairn Inria Socrate CEA Leti CEA List Inria Corse

Figure: ZEP Teams involved with their correspondants scientists.

I Inria Socrate (Leader, https://team.inria.fr/socrate/): embedded system design,

communication systems, operating systems and memory management [1].

I Inria Cairn (https://team.inria.fr/cairn/): energy-efficient system-on-chip and reconfigurable

architecture, energy harvesting [2], compilers and design tools.

I Inria Pacap (https://team.inria.fr/pacap/): compiler optimization, compilation-time energy

evaluation.

I Inria Corse (https://team.inria.fr/corse/): link between compilation and runtime. I CEA Leti (Lisan, http://www.leti-cea.fr/): ultra-low power IOT platform [3].

I CEA List (Lialp, http://www-list.cea.fr/): just-in-time compilation.

Expected Results

After 4 years, the project should have achieved the following:

I A NVRAM based platform demonstrator powered by harvesting.

I An innovating NVRAM based processor architecture designed for VLSI integration. I A solid system-level simulator for a generic NVRAM platform.

I A compiler leveraging WCEC (Worst Cases Energy Consumption) analysis.

I A primitive operating system including NVRAM management techniques and power management

policies.

I Publications of course...

I Lobbying, communication, new research directions etc.

References

[1] Gautier Berthou, Tristan Delizy, Kevin Marquet, Tanguy Risset, and Guillaume Salagnac. “Peripheral state persistence for

transiently-powered systems”. In: IoENT 2017 - 1st Workshop on Internet of Energy Neutral Things. Geneva, Switzerland, June 2017.

[2] Olivier Berder and Olivier Sentieys. “PowWow: Power Optimized Hardware/Software Framework for Wireless Motes”. In:

Workshop on Ultra-Low Power Sensor Networks (WUPS), co-located with Int. Conf. on Architecture of Computing Systems (ARCS 2010). Hannover, Germany, Feb. 2010, pp. 229–233.

[3] Edith Beign et al. “L-IOT: a Flexible Energy Efficient Platform Targeting Wide Range IoT Applications”. In:

ACM/EDAC/IEEE Design Automation Conference (DAC). Austin, TX, 2017.

Work Packages

CPU NVRAM

NVRAM-based micro architecture

Radio Sensors Low-res camera Energy buffer Harvester Light Harvester Warmth Harvester Radio waves Energy harvesting Memory Manager Energy Manager Operating system Compiler Sensing application Video decoding application Crypto application HW SW CEA LETI Inria Cairn Inria Socrate CEA LIST Inria Corse Inria Pacap

Figure: Overview of the ZEP resulting prototype

Task1: NVRAM-based Architecture

I NVRAM technology study: This expertise is mandatory to always consider that the proposed

non-volatile processor is feasible in terms of technology

I NVRAM-based sensor node platform: Replacing the PowWow [2] micro-controller (currently an

MSP430) by an FRAM-based MSP430FR5739 will provide a first and quickly available prototype.

I NVRAM-based processor architecture: we propose a collaboration between Cairn and CEA Leti to

explore new techniques at architectural and design level to store the intermediate computation states before power failures occur, through architecture improvements. The core of the micro-architecture will be based on a RISC-V processor (https://riscv.org/), and we will use CEA Leti experience on the L-IOT architecture [3].

Task 2: Compiler Optimizations and Worst-Case Energy Consumption

I Energy Model: we will derive a precise energy model of a NVRAM-based processor.

I Code Generation: we will provide a Worst Case Energy consumption (WCEC) driven code generation . I Checkpoints: The code generator could influence the checkpointing strategy.

I Quality of Service and Approximate Computing: We will also explore many ways to reduce

energy consumption when the battery runs low.

Task 3: Runtime memory management

I Provide support to the NVRAM architecture: the runtime system will have to share the

non-volatile memory across the various applications, according to their needs and priorities.

I Choose how energy is used energy policy must define the way the system should spend the available

energy depending on the length of each task to execute for instance.

I Ensure memory consistency: problems to be solved: processor state is volatile, devices’ states are

volatile and a priority between applications when saving data of must be established [1]. Task 4: Experimental platforms and use cases

I Use cases: Use cases will include a sensing application, a cryptography application, and a video

decoding application.

I Experimental platform: the ZEP prototype will consist in the integration of recent FRAM

MSP430 from Texas Instrument (MSP430FR5739 for instance) integrated in a new version of the PowWow sensor [2] node in which an the Actel Igloo FPGA also includes NVRAM.

I Simulation platform: for more advanced design issues, we will use simulation tools provided by CEA