rMODEM CoNffio~N'T
I. OFF-LINE
5.3 TOGGLE-IN PROGRAM
This test exercises a synchronous line in system test mode (11) using Sync A = 226.8 bits per character,
When toggling in this program, the operator should deposit the address of the DVll System Control reg-ister in location 1000 and deposit the line number under test in address 1002. After loading the test, set 1004 in the console switches, depress LOAD ADDRESS, and depress START.
1000 Zero this register
Decrement register counter Select RX Current Address Load RX Current Address
1132 112712 Select RX Byte Count
1134 5
1136 12713 Load -1 RX Byte Count
1140 177777
1142 112712 Select Line State Register
1144 13
1146 12713 Load Transmit GO
1150 4
1152 112712 Select TX Control Table Base Address
1154 10
1156 12713 Load TX Control Table Base Address
1160 2000
1162 112712 Select RX Control Table Base Address
1164 11
1166 12713 Load RX Control Table Base Address
1170 2000
1172 12760 Load LCR with Systems Mode, Receiver Enable, Strobe
1174 134000
1176 4
TEST: 1200 5760 Test for LCRI5=0; When true fall through
1202 4
1204 100775
1206 5210 Set Microprocessor Go
WAIT: 1210 105710 Test for Receiver Interrupt in DVSCR
1212 100376
1214 22737 Compare expected 227 vs stored character
1216 227
1220 1236
1222 1401 Branch to jmp if compare was equal 1224 0 Halt if comparison not equal
1226 137 Jump to MRESET
1230 1040
TXPCA: 1232 113226 Sync, sync
1234 227 I>ata CJ1aracter
RCVBUF: 1236 0 Received CJ1aracter
VI
Static Tests of DVll Functional Units (DZDVF)
x x x x x x
e.
~
U N I B U S
:.
U N I B U S
7
NEW SYNC DATA SET READY TERM ROY CS
co
RS RING
/~
r - - - LINES 0- 3 1
DV11 LINES 4- 7
"-MODEM H861
CONTROL LINES 8 -11 (16 LINES) UNIT LINES 12-15
'
-Figure 5-6 Test Configuration
(DVII Modem Control Unit with H861) Block Diagram
H 325 24 SCE = : £ 8 5 SCT f7 SCR SEC XMIT 11
SEC RCV
~
XMIT DATA
- 4
RCVDATA ~
~;=*
CO
==u
14
I 1 1 1
( I H8 61 FO R ONE
E LIN
11- 2 936
NEW SYNC
~
CUT TO TEST*20 NEW SYNC 22
DATA SET ROY
DTR
LINES 0-3 DVll LINES 4-7
MODEM DISTRIBUTION
CO~~WL I - -L_I_N_ES_S-_l_' _ - I PANELS LINES 12-'5
15 [QJ MODEM TEST CONNECTOR (H325)
NOTES:
OISTR I BUTION PANEL EIA CONNECTOR
P. GND
E IA XM IT DATA .00 EIA RCV DATA 00 RTS 00
CTS 00
S GND CARRIER 00
(202 SEC TX ( 0 ) NEW
~~---~-O~-SYNC
W02A .00
W06S DCE SCT 00 W07S
__ ~---~-o---DCE SCR 00
DTR .00
RI 00 W04S
_ _ ~---___('~o_-DTE SCTE 00
__ f - - - ' O - - O - - - RTS 00 W05F
1. Jumper configuration is typical for remaining lines.
For actual jumper locations, refer to drawing D-CS-5411153.
2. For asynchronous use, remove jumpers denoted by the letter "S".
H325
TEST CONNECTOR Jl-2 - - -.... 1 J 1-3 _ _ _ --I.
J1-4~
J 1-5
J 1-8
J1-11---_·1 J1-12 - - - I .
J1-15~
J1-24 Jl-17
J120 -J 1 - 22 - - - ' I
( NEW*
SYNC ( "A"
J 1- 6 ---i J1-14---'
*NORMALLY REMOVED
For synchronous use, remove jumpers denoted by the letters "A" or "r"
11-4404
Figure 5-8 Distribution Panel and Test Connector Jumper Configuration
.t. ~
REMOTE 0 I
t-
PDP-ll SYSTEMI I MODEM OR TEST
I STATION
LINE 0-3 I
U I
N DV11 LINE 4-7 I
I MODEM DISTRIBUTION I
B CONTROL LINE 8-11 PANELS
U UNIT I r - - - - ..,
S LINE 12-15
I I L ____ ...J
1---I
r----.
15 I
L ____ --1
"Ii '7
11-293'1
Figure 5-9 Test Configuration (ON LINE Modem Loop-Back) Block Diagram
Table 5-6
System Control Register Maintenance Bits
Bit(s) Designation Function Read/Write
00 Microprocessor Go When set to one, enables the Microprocessor to Read or Write operate the DVll Data Handling Section. Must
be set to one to enable DVl1 to perform any functions oth~r than modem control. Cleared by Initialize.
01 ROM Single Step When set to one, causes the DVll microprogram to Read or Write execute one Read Only Memory cycle and stop.
When the ROM cycle begins, this bit is automatically cleared. Geared by Initialize.
02 ROM Branch Disable When set to one, inhibits execution of branch instruc- Read or Write tions by the Microprocessor. Geared by Initialize.
03 ROM Data Source When set to one, enables loading of the Special Read or Write Select Functions Register (SFR) by the PDP-II program.
The contents of the SFR are then automatically strobed intothe ROM Data Register, a Microprocessor register. Cleared by Initialize.
09 Bits 07 and 15 When set to one, places the DVl1 in System Read or Write Write Enable Maintenance mode, enabling the DVll program
to write bits 07 and 15 of this register (SCR 15).
Cleared by Initialize. The System Control Register must be word addressed when and while these bits
Bit(s) Designation 00-01 Microprocessor Branch
True L
(Bit 00 - Branch A) (Bit 01 - Branch B)
07 Maintenance Bit Window
08 Maintenance Clock Pulse
09 Transmitter Disable
11,12 Maintenance Mode Select
Table 5-7
Line Control Register Maintenance Bits (F or Synchronous Line Cards)
Function
Whenever a branch instruction is encountered by the Microprocessor and the point tested by the Micro-processor is true, the branch is enabled and one of these bits will clear. Bit 00
=
0 if a Branch A instruc-tion causes a branch, and bit 01=
0 if a Branch B instruction causes a branch. (Microinstructions are described in Section 4.7.)This bit displays the input bit stream to the receiver for the line selected by SRS 00-03. If LCR 09 (Transmitter Disable) is set to zero for the selected line, the output of the selected line's transmitter will be the input data.
If LCR 09 was set to one and maintenance mode 01 was set in LCR 11, 12 for the selected line at bit 15 set time, the Maintenance Data bit (LCR 14) will be the input data.
Simulates the transmitter and receiver clocks for every line for which maintenance mode 01 was set in LCR 11, 12 at LCR 15 set time. When set to one, causes maintenance mode 01 receivers to input one bit each and causes the corresponding transmitters to output one bit each LCR 08 then clears itself. BIS and BIC instructions should not be used to set this bit.
When set to one, disables the transmitter for the 4-line group selected by SRS 02-03 at LCR 15 set time.
This permits entry of Maintenance Data from LCR 14 to the receivers for the selected lines without inter-ference from the lines' transmitters.
For the 4-line group selected by SRS 02-03, these bits set normal operation or one of the three maintenance modes at LCR 15 set time, as follows:
Mode 12 11
Normal Operation 0 0
Internal Maintenance Mode 0 1 External Maintenance Mode 1 0 Internal Maintenance Mode 1 1
for System Testing
LCR 11, 12 are cleared by Initialize. Maintenance modes are described in Section 5.1 .
Read/Write Read
Read only
Write
Write
Write
Bit(s) Designation 14 Maintenance Data
15 Control Strobe
Table 5-7 (Cont)
Line Control Register Maintenance Bits (For Synchronous Line Cards)
Function
When set to one at LCR 15 set time, simulates data at the input to the receivers for the 4-line group set in SRS 02--03, provided that mainte-nance mode 01 has been set for those lines (see LCR 11, 12 description).
If LCR 14 is being used to simulate receiver data, LCR 09 (Transmitter Disable) should be set to one for the selected lines at LCR 15 set time to inhibit additional input from the transmitters.
LCR 14 should be cleared when not in use for simulating input data. Cleared by Initialize.
When set to one, strobes LCR 13 into control storage for the line set in SRS 00-03 and sets LCR 09, 10, 11, 12, 14 into control storage for the 4-line group set in SRS 02-03, then clears itself. May be set at the same time as the LCR bits that it strobes into storage for the selected line or line group.
Read/Write Write
Write
Bit(s) Designation 00-01 Microprocessor
Branch True L (Bit OO-Branch A) (Bit 01-Branch B)
09-10 Maintenance Register Selection Code 11
11 Maintenance Internal Mode
15 Control Strobe
Bit(s) Designation
08 STEP
09 MAINT MODE
(Maintenance Mode)
Table 5-8
Line Control Register Maintenance Bits (For Asynchronous Line Cards)
Function
Whenever a branch instruction is encountered by the Microprocessor and the point tested by the Microprocessor is true, the branch is enabled and one of these bits will clear. Bit 00 = 0 if a Branch A instruction causes a branch, and bit 01 = 0 if a Branch B instruction causes a branch. (Microinstructions are described in Paragraph 4.7.)
For the line number selected by SRS 00-03, the code of 11 specifies writing into the Maintenance register at LCR 15 set time. Cleared by Initialize.
This bit, when set, loops the transmitter's serial output lead to the receiver's serial input lead. While operating in Maintenance mode, the EIA transmit data leads, EIA received data leads, and the remote Data Set Busy features are disabled. Normal operating mode is assumed when this bit is cleared. Cleared by Initialize.
When set to a one, strobes the Maintenance register bit 11 into storage for the line specified in SRS 00-03, then clears itself. May be set at the same time as the bit that it strobes into storage.
Table 5-9
Control Status Register Maintenance Bits Function
When set to 1, causes the line number in CSR 00-03 to be incremented by 1. If a status transition is detected for the new line, Done (CSR 07) is set to 1.
Done does not inhibit Step. This bit is used principally for maintenance and requires 1.2 microseconds ± 10%
to execute. This bit is write ones only.
When set to 1, causes all status lines from all enabled modems to be logical ones. Used for maintanence.
Cleared by Initialize and Clr Scan (CSR 11).
ReadfWrite Read
Write
Write
Write
Read/Write Write ones
Read or Write
The PDP-II memory is organized into I6-bit words consisting of two 8-bit bytes. Each byte is addressable and has its own address location: low bytes are even-numbered, high bytes are odd-numbered. Words are addressed at even-numbered locations only and the high (odd) byte of a word is automatically included to provide a I6-bit word. Consecutive words are there-fore found in even-numbered addresses. A byte oper-ation addresses an odd or even locoper-ation to select an 8-bit byte.
The Unibus address word contains 18 bits identified as A(l7:00). These 18 bits provide the capability of addressing 256K memory locations, each of which is an 8-bit byte. This also represents 128K 16-bit words.
In this discussion, the multiplier K equals 1024 so that 256K represents 262, 144 locations and 238K rep-resents 131,072 locations. This maximum memory size can be used only by a PDP-ll processor with a Memory Management Unit that utilizes all 18 address bits. Without this unit, the processor pro-vides 16 address bits which limits the maximum mem-ory size to 64K (65,536) bytes or 32K (32,768) words.
Figure A-I shows the organization for the maximum memory size of 256K bytes. In the binary system, 18 bits can specify 218 or 262,144 (256K) locations. The octal numbering system is used to designate the address. This provides convenience in converting the address to the binary system that the processor uses, as shown below.
17 16 15 14 13 12 11 10 09 08
0 0 1 0 0 1 1 1 1 1