II
A.C. PERFORMANCE
The cell library provides the maximum delay time for worst case technology, 2!i"C ambient and VCC = -5.2 V.
Worst case performance can be calculated using the for·
mula provided in the design manual or the CAD sys·
tem.
The CAD system provides the designer with both a prerouting and routed A.C performance simulation.
The prerouting simulation is based upon statistical loading estimates based upon fanout.
The designer can also calculate the typical and best case performance by multiplying worst case performance by 0.5 and 0.7 respectively.
The designer will be able to select the speed power pro-ducts of an intemal macro. Each function, where possible, will be released using a 0.300 mA and 0.600 mA source current. By doubling the power, the designer is able to obtain a 30 % performance improvement.
Table 1 provides a summary of typical performances for selected intemal and I/O logic functions. The inter·
nal macros performance does not vary based upon in·
terface mode.
TABLE 1 - TYPICAL TIMING DELAYS INTERNAL MACRO (1) TYPICAL DELAY
3 Input gate 1.8 ns
Other packages available on request.
QUALITY LEVELS
In addition to the standard quality procedures for commercial grade product, "!HOMSON SEMICON·
DUCTEURS offers a variety of extended temperature ranges and high reliability screening levels for the TSC MACRO Arrays. All extended screening is performed at
"!HOMSON SEMICONDUCTEURS' Military and Spatial Division facility in France, which is completely equip·
ped with state·of·the·art assembly, electrical test and en·
vironmental stress equipment. The Military and Spatial Division is dedicated to performi ng quality control and reliability assurance for all "!HOMSON SEMICONDUC·
TEURS integrated circuits for mil.itary and space ap.
AVAilABLE SCREENING LEVELS
le",,1 Description
Standard Commercial Temp. Range 0° to+ 70°C Industrial Temp. Range -40° to+ 85° C Military Temp. Range _55° to+ 125°C D Standard Level with Burn·in
B/B Full MIL-STD·883C, Class B Screening G/B MIL·STD·883C Without Constant Accele·
ration or Temp. Test, PDA< 10 %.
THOMSON SEMICONDUCTEURS
186
CAD SYSTEM
All of the lHOMSON SEMICONDUCTEURS Array Products are supported by a fully automated VAX/
VMS based CAD System. The CAD System provides a complete set of industry standard design, layout and verification tools to ensure fast, error·free design of the TSC MACRO ARRAYS. The CAD System resides at lHOMSON SEMICONDUCTEURS Design Center and is accessed with a Tektronix 4109 (or equivalent) graphics terminal.
The CAD System can also accept verified netlists from a variety of popular engineering workstations, including DaiSY® , Valid® ,Mentor®, and IBM PC·XT®. based workstations that are equipped with the TSC Series Macro library. The key components of the lHOMSON SEMICONDUCTEURS CAD System are :
Schematic Capture Netlist Extraction Logic Simulation Timing Analysis
Fault Grading T ester Program Interface Automatic Placement and Routing Interactive Placement and Routing Design Rule Checking
Automatic Mask Generation
SDS®
®SDS and GARDS are trademarks of SilvarLisco. HILO is a trade-mark of GenRad Inc. VAX Wid VMS are tradetrade-marks of Digital Equipment Corp. IBM and Pc;.XT are trademarks of the IBM Corporation. Daisy is a trat:Bmark of Daisy Systems Corp.
Mentor is a trademark of Mentor GrEPhics Corp. Valid is a tra-cemark of Valid Logic SYS1BmS Inc.
DESIGN DEVELOPMENT PROCEDURE
Design entry is easily accomplished with the SDS menu driven software and a graphics terminal (Tek 4109). The SDS generated logic schematic is converted to a nettist and checked for logic design rule violations (excessive fanout, for instance). The netlist is then automatically converted to HILO simulation format.
The HI LO simulation program performs logic simulation based on the user defined input test pattern and timing analysis using pre·routing statistical load capacitances for delay calculations. HILO also can be used to perform fault grade analysis of the input test pattem.
The GARDS program is used to automatically place and route the array's cell logic as described in the SDS netlist.
GARDS also has an interactive mode that allows cell or I/O preplacement and manual routing to optimize critical paths if necessary. After placement and routing is com·
pleted, HI LO timing analysis can be performed again to determine worst case critical path delays using the actual interconnect length and fanout capacitances.
When the array design work is completed on the CAD System, the HI LO simulation output is automati·
cally converted to a tester program tape and the GARDS place and route file is converted to a graphics data base for mask generation. These two data bases are then sent to the factory for prototype generation.
The design of an array option is a joint development effort involving lHOMSON SEMICONDUCTEURS and the CUSTOMER. lHOMSON SEMICONDUCTEURS offers a very flexible interface to the CAD System, providing the CUSTOMER with several options in performing the various CAD Development Procedures as shown below:
I I
lliOMSON SC CAD SYSTEM CUSTOMER DESIGN TASKS
Logic/System Description Arrflol Selection/Partition
Macro Logic Convenion Schematic Captu re
Test Pattern Input' Targat Specification Definitionl
I
Input Test Pattern Description' Logic/Simul mionTiming Analysis Fault Grading
t
CUSTOMER DEVELOPMENT OPTIONS Pre-Plarement
r -I - Auto Place/Route L - - l TURNKEY DESIGN. The CUSTOMER develops Final Logic Simulation
t~
the system logic schematic and functional
cescrip-tion of the circuit. lHOMSON SC conver1S the Worst Case Timing Analysis TOME R generates a macrocell system schematic
L-and description of input test vectors. lHOMSON SC transfers this input to the CAD System and ccmpletes the CAD Development.
3 WORKSTATION INPUT. Using one of the pq,ular engineering workstations (DAISY. VALID. MEN-,OR. PC-XT) and the appropriate lliOMSON SC Cell Library, the CUSTOMER generates a macro-cell schematic and perfOITTlS various simulation work dependng on the workstation used The resulting verified nertist and input test pattern is transferred to the CAD System and lHOMSON S completes the CAD Development.
717
NOTES
This is advance information and specifications are subject to change without notice.
Please inquire with our sales offices about the availability of the different packages.