OPERATING RANGE

-Note: [P, +G,P, +G,G, Po +G2G, GoCnl ' f [P3 +G3P,+G3G2P, +G3G2G, Po +G3GiG, GoCnl Figure 8.

MAXIMUM RATINGS

(Above which the useful life may be impaired) Storage Temperature

Temperature (Ambient) Under Bias Supply Voltage to Ground Potential

DC Voltage Applied to Outputs for HIGH Output State DC Input Voltage

DC Output Current, Into Outputs DC Input Current

Part Number Suffix CSUFFIX

M SUFFIX

Vee Temperature

4.75V to 5.25V TA = ooe to +70oe

4.50V to 5.50V Tc = -55°e to +125°e

Figure 9

8/24

THOMSON SEMICONDUCTEURS

See note + =: OR

-0.5 V to +7.0 V -0.5 V to +Vcc max.

-0.5 V to +5.5 V 30mA -30 mA to +5.0 mA

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)

ICC Power Supply Current

VCC=

'"

rA=+70"C 220

(Note 5) TC = _55°C to mA

MIL Only .+'25°C 280

TC = +'25"C '98

Notes: 1. Vee conditions shown as MIN or MAX, refer to the military (±10%) or commercial (±S%) Vee limits.

2. Typical limits are at Vee = S.OV. 25°C ambient and maximum loading.

3. Not more than one output should be stored at a time. Duration of the short circuit test should not exceed one second.

4. These are three· state outputs internally connected to TTL inputs. Input characteristics are measured with 1678 in a state such that the three·state output is OFF.

5. Worst case Icc is measured at the lowest temperature in the specified operating range.

6. These input levels provide zero noise immunity and should only be tested in a static. nOise-free environment.

9/24

THOMSON SEMICONDUCTEURS

If7

•

I. 2901C Guaranteed Commercial

A, Cycle Time and Clock Characteristics,

Range Performance

The tables below specify the guaranteed performance of the 2901 C over the commercial operating range of O·C to + 70·C with VCC from 4.75V to 5.25V. All data /Ire in ns, with inputs' switching between OV and 3V at Wins and measurements made at 1.5V. All outputs have maximum DC load.

Read-Modify-Write Cycle (from selection of A, B registers to end of cycle.)

Maximum Clock Frequency to shift Q (50% duty cycle, I

=

432 or 632)

Minimum Clock LOW Time This data applies to the following part numbers: Minimum Clock HIGH Time

TS2901C CP TS2901CCJ

Notes:

Minimum Clock Period

B, Combinational Propagation Delays.

CL = 50pF

C. Set-up and Hold Times Relative to Clock ICP) Input.

Input

D. Output Enable/Disable Times, Output disable tests performed with CL = 5pF and

measured to 0.5V change of output voltage level.

Input Output Enable Disable

OE y 23 23

1. A dash indicates a propagation delay path or set-up time constraint does not exist.

RAMO 00

2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation. This is indicated by the phrase "do not change", 3. Source addresses must be stable prior to the clock H -+ L transition to allow time to access the source data before the latches close. The A

address may then be changed. The B address could be changed if it is not a destination; i.e. if data is not being written back into the RAM. Normally A and B are not changed during the clock LOW time.

II. 2901C Guaranteed Military

A. Cycle Time and Clock Characterl.tlcs.

Range Performance

The tables below specify the· guaranteed performance of the 2901C over the military operating range of-55°C to + 125"C, with Vee from 4.5V to 5.5V. All data are in ns. with inputs switch-ing between OV and 3V at Wins and measurements made at 1.5V. All outputs have maximum DC load.

Read·Modify-Write Cycle (from selection 01 A. B registers to end 01 cycle.)

Maximum Clock Frequency to shift Q (50% duly cycle.

This data applies to the following part numbers:

TS2901CMJ TS2901C ME

I - 432 or 632) Minimum Clock lOW Time Minimum Clock HIGH Time Minimum Clock Period

B. Combinational Propagation Delays.

=

^SOpF

C. Set-up and Hold Times Relative to Clock (CP) Input.

Input D. Output Enable/Disable Times.

Output disable tests performed with CL

=

5pF and measured to 0.5V change of output voltage level.

Input Output Enable Disable

OE y 25 25

1. A dash indicates a propagation delay path or set~up time constraint does not exist.

2. Certain signals must be stable during the entire clock lOW time to avoid erroneous operation. This is indicated by the phrase "do not change".

3. Source addresses must be stable prior to the clock H -+ L transition to allow time to access the source data before the latches ctose. The A address may then be changed. The B address could be chsnged ij ~ is not a destination; i.e. if data is not being wriUen back into the RAM. Nonnelfy A _ B ... _ chllnged during the clock LOW tI ...

4. The set-up time prior to the clock L .... H transition is to allow time for data to be accessed. passed through the ALU. and retumed to the RAM. It includes 21=1 the time from stable A and B addresses to the dock L -+ H transition, rega~less of when the clock H -+ L transition occurs.

11/24

THOMSON SEMICONDUCTEURS

II

TTL INPUT/OUTPUT CURRENT INTERFACES

MET SCHOTTKY

DRIVEN INPUT DRIVEN INPUT

PHP DRIVEN INPUT

~C---.---~---~---"H

en 2k

00.3. RAMo, 3 15k

THREE-STATE OUTPUT

500 NOM

13.4.5,7 10k 10,1,6,8 20' OJ!

20.

00., 10k

=

5.0pF, all inputs

NORMAL

son NOM

[

F

=

5.0pF, all outputs

12/24

THOMSON SEMICONDUCTEURS

I'H

CP I,

Ao-a. B0-3

OPEN COLLECTOR OUTPUT

6k 10k 6k

F=O

TEST OUTPUT LOAD CONFIGURATIONS FOR 2901C

A. THREE-STATE OUTPUTS B. NORMAL OUTPUTS

<:.

OPEN-COLLECTOR OUTPUTS Vee

I

_s,

s, ^R,

VOUT ~o-... - ... -,K~-4 s,

VOUT ~>-... - ...

-I<1--'" R,

A, ~ 5.0 - VeE - VOL 5.0 - VeE - VOL

A, ~ ---~=--~

5.0 - VOL A, ~

IOl

Notes: 1. CL = 50pF includes scope probe. wiring and stray capacitances without device in test fixture.

2. 81, 82, 83 are closed during function tests and aU AC tests except output enable tests.

3. 81 and 53 are closed while 82 is open for tpZH test.

8 1 and 82 are closed while 83 is open for tpZL test.

4. Cl ~ 5.0pF for output disable tests.

Pin"

3 5 7 13 18 28 29 30 31 32 33·36

TEST OUTPUT LOADS FOR 2901C

Test Pin Label Circuit R,

AAM3 A 560

AAMo A 560

F ~ 0 C 270

03 ^A 560

00 A 560

F3 B 620

G B 220

Cn+4 B 360

OVA B 470

P B 470

YO-3 A 220

13/24

THOMSON SEMICONDUCTEURS

R2 ,K 1K -1K 1K 3.9K 1.5K 2.4K 3K 3K 1K

MINIMUM CYCLE TIME CALCULATIONS FOR l6·BIT SYSTEMS Speeds used in calculations for parts other than 2901C are

representative for available MSI parts.

LSB A,S,I,en

0

2901 C

.Jl.J

CLOCK

Plpellned System. Add without Simultaneous Shift.

r-+ 2901C + 3 2902A + 4 2901C + 5 Register

DATA LOOP

Clock to Output 9

A.BtoG,P 37 + 6 MUX

Go.

^{Po to C}nH 10 + 7 2910

Cn to Cn+_4•OVR. F3. F ⁼O. Y 25

~~~'

+ 8 PROM + 1 Register

Set·up Time 2

83ns

Minimum clock period = 109ns

14/24

THOMSON SEMICONDUCTEURS

CONTROL LOOP Clock to Output Select to Output CC to Output Access Time Set·up Time

CD ~ffi

Iii:;: ~~

_a:

9 13 45 40 2 109n5

MINIMUM CYCLE TIME CALCULATIONS FOR 16-BIT SYSTEMS (Cont.) Speeds used in calculations for parts other than 2901C are

representative for available MSI parts.

LSB

® . . .

RAMOQDRAM3---A.B.I.Cn G.p

2901C

...f1..J

CLOCK

C!2MSB

RAMO RAM3

2901C

Pipelined System. Simultaneous Add and Shift Down.

DATA LOOP CONTROL LOOP

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