The TS2917A is a high-performance, low-power Schottky bus trans-ceiver intended for bipolar or MOS microprocessor system applications.
The device consists of four Ootype edge-triggered flip-flops. The flip-flop outputs are connected to four three-state bus drivers. Each bus driver is internally connected to the input of a receiver. The four receiver outputs drive four Ootype latches, that feature three-state outputs. The device also contains a four-bit odd parity checker/generator.
The LSI bus transceiver is fabricated using advanced low-power Schottky processing. All inputs lexcept the BUS inputs) are one LS unit load. The three-state bus output can sink up to 48 rnA at 0.5 V maximum. The bus enable input IBE) is used to force the driver outputs to the high-impedance state. When BE is HIGH, the driver is disabled.
The input register consists of four Ootype flip-flops with a buffered com-mon clock. The buffered comcom-mon clock IORCP) enters the Ai data into this driver register on the LOW-to-HIGH transition.
Data from the A input is inverted at the BUS output. Like-wise, data at the BUS input is inverted at the receiver output. Thus, data is non-inverted from driver input to receiver output. The four receivers each feature a built-in Ootype latch that is controlled from the buffered receiver latch enable
The TS2917A features a built-in four-bit odd parity checker/generator.
The bus enable input IBE) controls whether the parity output is in the generate or check mode. When the bus enable is LOW Idriver enabled), odd parity is generated based on the A field data input to the driver regis-ter. When BE is HIGH, the parity output is determined by the four latch outputs of the receiver. Thus, if the driver is enabled, parity is generated and if the driver is in the high-impedance state, the BUS parity is checked.
• Quad high-speed LSI bus-transceiver
• Three-state bus driver
• Ootype register on driver
• Bus driver output can sink 48 rnA at 0.5 V max.
• Internal odd 4-bit parity checker/generator
• Receiver has output latch for pipeline operation
• l'hree-state receiver outputs sink 12 rnA
• Advanced low-power Schottky processing
• 3.5 V minimum output high voltage for direct interface to MOS
WITH INTERFACE LOGIC
CASECB-194 Hi-Rei versions atailable - See chapter 4
PIN ASSIGNMENT
DRIVER DRCP CLOCK BUS ENABLE BE
19
9 11
LOGIC SYMBOL
3 13 17
AO Al A2 A3
DRCP ODD 10
RLE RO
TS2917A Rl 8
BE R2 12
DE R3 18
BUSo BUSI BUS2 BUS3
4 6 14 16
VCC • Pin 20 GNDI 'Pin 5 GND2 = Pin 15
'---o(:J--ORLE
~!~~:.:'ER
ENABLE
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature _65°C to +150°C
Temperature (Ambient) Under Bias _55°C to +125°C
Supply Voltage to Ground Potential -0.5 V to +7 V
DC Voltage Applied to Outputs for HIGH Output State -0.5 V to +VCC max.
DC Input Voltage -0.5 V to +7 V
DC Output Current, Into Outputs (Except _B_U_S_) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3,-0:c-mA
DC Output Current, I nto Bus 100 mA
DC Input Current -30 mA to +5.0 mA
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ELECTRICAL CHARACTERISTICS
The following conditions apply unless otherwise noted;
CSUFFIX (COM'LI TA=O°Cto+70oC VCCM1N.=4.75V VCCMAX.=5.25V M SUFFIX (MIL) T A'" -5S"C to +f2SoC VCCMrN. = 4.50V Vee MAX. '" 5.50V
BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
Parameters Description Test Conditions (Note 1)
Bus Output LOW Voltage
I
tOl - 24mAVIL Receiver Input LOW Threshold Bus enable'" 2.4 V
I
MILVee MAX.
Ise Bus Output Short Circuit Current
VO' OV
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Parameters Description IIH Input HIGH Current (Except Bus) II Input HIGH Current (Except Bus) Ise Output Short Circuit Current
(Except Bus) lee Power Supply Current 10 Off·State Output Current
(Receiver Outputs) Guaranteed input logical HIGH
for all inputs
Guaranteed input logical LOW MIL
for at! inputs eOM'L
ELECTRICAL CHARACTERISTICS
The following conditions apply unless otherwise noted:
C SUFFIX (COM'LI M SUFFIX (MI LI
TA '" O"'C to +70°C VCCM1N. '" 4.75V Vee MAX. '" 5.25V TA=-55LCto+125°C VCCM1N.=4.50V VCC MAX .=5.50V
SWITCHING CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
MSUFFIX CSUFFIX
Parameters Description Test Conditions Typ.
Min. (Note 2)
Typ.
Max. Min. (Note 2) Max.
tpHL 21 36 21 32
tPLH Driver Clock (ORep) to Bus
CL (BUSI = 50pF 21 36 21 32
tZH. tZL
Bus Enable (BE) to Bus
RL (BUS) = 130" 13 26 13 23
tHZ. tLZ 13 21 13 18
ts 15 12
A Data Inputs
th 8.0 6.0
tpw Clock Pulse Width (HIGH) 20 17
tPLH Bus to Receiver Output 18 33 18 30
tPHL (Latch Enabled) 18 30 18 27
tPLH 21 33 21 30
Latch Enable to Receiver Output
tpHL 21 30 21 27
ts 15 13
Bus to Latch Enable (RLE) CL = 15pF
th 6.0 4.0
- -
RL = 2.0kntpLH A Data to Odd Parity Out 32 46 32 42
tPHL (Driver Enabled) 26 40 26 36
tpLH Bus to Odd Parity Out 21 36 21 32
tpHL (Driver Inhibit) 21 36 21 32
tPLH Latch Enable (RLE) to Odd 21 36 21 32
tpHL Parity Output 21 36 21 32
tZH. tZL 14 26 14 23
Output Control to Output
tHZ.tLZ CL -5pF. RL -2.0kn 14 26 14 23
Notes:
Units ns
ns
ns ns ns
ns
ns
ns
ns
ns
ns
1. For conditions shown as MIN. or MAX .• use the appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical limits are at Vce '" 5.0 v. 25° e ambient and maximum loading.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
DRIVEN INPUT 17 kn
INPUT o-~-fQ-4-1DJ----,~
J
INPUT/OUTPUT CURRENT INTERFACE CONDITIONS
. Note: Actual current flow direction shown.
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INPUT A OR INPUT B
DRIVER CLOCK
A INPUT
BUS OUTPUT
RECEIVER OUTPUT
TS2911A
BUS
f
SWITCHING TEST CIRCUIT
TEST POINT
SWITCHING WAVEFORMS
\ f
I"t'"-I I
~
tPLH-It= fIII//////// tPHL~
*CL:= 15pF for tpLH. tpHL.
tZL, tZH CL'= 5pF for tHZ. tLZ
3.0V 1.3 V OV 3.0 V
~
OV 1.3 Vf-
VOH1.3 V
I t
t P H L B tpLH
--I 1-:=
VOL\ F
VOH VOL 1.3VNote: Bus to Receiver output delay is measured by clocking data into the driver register and measuring the BUS to R combinatorial delay.
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I/O in high speed Microprocessor Systems.
Aj
No drive!" clock restrictions
X X