System Interface

Table 2-8. System Interface Signals Signal Name MCM Nodes Description

IGN_PCI_AD31 AD01 U2.57 I 660 Ignore PCI_AD[31] input. This signal is required when the Intelt SIO is the PCI master, because it does not latch ISA_MASTER on posted ISA writes to 0 to 16M. IGN_PCI_AD31 is used to allow ISA busmasters to access system memory when the SIO is used as the ISA bridge. The 664 expects the memory address to appear in the range of 0 to 16M (it actually works over the entire 0-2G range) during the address phase when IGN_PCI_AD31 is asserted and then maps the access to system memory at 0 to 16M. It is usually generated by ANDing all of the active PCI bus grants (see note 1). IGN_PCI_AD31 must be valid on the PCI clock before FRAME# is sampled active.

664_STOP_CLK_

660 input. Prepares the 660 for stopping the CPU_CLK during power management. This feature is not supported. Leave this pin pulled high for normal operation.

Exceptions

INT_TO_664 B31 U2.55 I 660 INT_REQ Interrupt request input. The 660 synchronizes this signal from the interrupt controller to the CPU bus clock and passes it through to the CPU as an interrupt.

INT_60X# U16 R1.D03

U1.188 pu I

CPU INT# Interrupt input. The CPU initiates an interrupt if MSR[EE] is set (603e), else it ignores the input. Active low, level sensitive, unlatched.

X_INT_60X# F31 U2.139 O 660 INT_CPU# CPU interrupt output. The 660 asserts INT_CPU# to signal the CPU to run an interrupt cycle. The software is expected to eventually run a PCI interrupt acknowledge transaction to get the interrupt vector. 660 can assert INT_CPU# in response to an INT_REQ input. Normally connected to INT_60X#

NMI_FROM_

ISABRDG

A31 U2.56 I 660 NMI_REQ input. Non–maskable interrupt request. When detected active (normally from the ISA bridge), an error is reported to the CPU.

POWER_GOOD/

RESET#

A28 U2.156 I 660 Power–On–RESET#. While this pin is low, all latches in the 664 enter a pre–defined state. Clocking mode is re-sampled, and ROM write lockout is cleared.

ROM

ROM_OE# V31 U2.47 O 660 ROM output enable. ROM_OE# enables direct-attached ROM.

This signal is always high during remote ROM operation.

ROM_WE# T31 U2.60 O 660 ROM write enable. Write enable for flash ROM for direct-attach ROM. This signal is always high during remote ROM operation.

GNT 0 . . GNT n

IGN_PCI_AD31

Section 2 — Signals

Table 2-8. System Interface Signals (Continued) Signal Name MCM Nodes Description

Daisy Chain

Daisy01 E04, D05 The DAISYxx columns are arranged in pairs which are connected to

h th F l D i 01 i t f l E04 d D05

Daisy02 E06, D07

g

each other. For example, Daisy01 consists of columns E04 and D05, which are connected to each other

Daisy03 E08, D09 which are connected to each other.

Daisy04 E10, D11

60X_AV_DD B02 U1.209 603e Analog VDD. Bypass as recommended in the 603e documentation.

These signals provide communication between the 663 and the 664. They are generally not intended for use by the system. Note that CPU_RDL_OPEN requires a resistor or other delay component between the 663 and the 664. For more information, see Section 2 of the 660 User’s Manual.

Table 2-9. InterChip Communication Signals Signal Name MCM Nodes Description

660 CPU_PAR_ERR# signal. CPU Data Bus Parity Error. When as-serted, this signal indicates a parity error on the CPU data bus during a write cycle.

AOS_RR_MMRS W20 U2.69 U3.166

O I

660 All Ones Select/ROM Remote/Mask MEM_RD_SMPL signal. This signal is used to force the data bus to 64 one-bits.

While ROM_LOAD is asserted, this signal is used to determine the location of the ROM.

When the PCI is burst reading memory, MASK_MEM_RD_SMPL is asserted after the first MEM_RD_SMPL, and stays asserted until the PCI–to–MEM read latch is empty.

Table 2-9. InterChip Communication Signals (Continued)

660 CPU–to–PCI Write Latch Open signal. When asserted, the CPU–to–PCI write latch accepts new data on each CPU_CLK. When deasserted, the CPU–to–PCI write latch holds its current contents.

CPU_DATA_OE# J14 U2.197 U3.146

O I

660 CPU Data Output Enable signal. When asserted, the 663 drives the CPU_DATA bus on the next CPU_CLK.

CPU_RDL_OPEN G12 U2.50 O 664 CPU Read Latch Open output. When asserted, the CPU read latch accepts new data on each CPU_CLK. When deasserted, the CPU read latch holds its current contents.

This signal is asserted when data is to be sampled from memory or the PCI.

When sampling data from memory, this signal is also active on the fol-lowing CPU_CLK to allow ECC corrections to occur if necessary. If no ECC corrections occur, the same data is provided by the MEM read ECC correction logic.

X_CPU_RDL_

OPEN

G10 U3.148 I 663 CPU Read Latch Open input. See the 660 User’s Manual for more information.

Add a 200 (nominal) series resister to the CPU_RDL_OPEN net between the 664 and the 663. During a CPU to memory read, if (at the 663) CPU_RDL_OPEN goes low before MEM_RD_SMPL goes low, then the 663 may provide incorrect data to the CPU. The Table shows the minimum required interval between the falling edge of MEM_RD_SMPL and the falling edge of CPU_RDL_OPEN.

Case 663 664

Requires Supplies 1 Worst Case Process, Temperature, & V_DD > 1.8ns 1.3ns 2 Best Case Process, Worst Case Temp. & V_DD > 0.2ns 0.5ns 3 Best Case Process, Temperature, & V_DD > 0.1ns 0.3ns The worst practical case occurs while the 664 is at Case 2 (provides .5ns difference) and the 663 is at Case 1 (requires 1.8ns difference). This re-quires that a minimum delay of 1.3ns be added to the CPU_RDL_OPEN signal. A delay of 2.4ns is recommended to allow a conservative margin of error. (Delay = RC = 200 * 12pf = 2.4ns). Note that this assumes the CPU_RDL_OPEN and MEM_RD_SMPL nets are both about three inches long and that the resister is close to the 664. A different resister value or an R-C combination may be required if the length or capaci-tance of the two nets are significantly different, or if the resister placement differs significantly.

CRS_C2PWXS A29 U2.65

U3.151 O I

660 CPU Read Select/CPU-to-PCI Write Crossover Select signal.

When the CPU read latch is sampling data, this signal controls the CPU read multiplexer.

When the CPU-to-PCI write latch is sampling data, this signal controls the CPU-to-PCI write crossover. Pull down with a 1K (nominal) resistor to select (during reset) direct-attach ROM.

DUAL_CTRL_REF N12 U2.205 U3.170

O I

660 Control Signal Mux Select signal. For 663 inputs that have two func-tions this signal selects the function. This signal is generated by dividing CPU_CLK by two. This is a useful first point to check when debugging a ”dead” system.

ECC_LE_SEL L12 U2.2

U3.149 O I

660 ECC Select/Little-Endian Select signal. This signal indicates use of ECC or byte parity when DUAL_CTRL_REF is high and indicates use of little-endian or big-endian mode when DUAL_CTRL_REF is low.

MEM_BE[3:0] U2. U3 O, I 660 Memory Byte Enables signal. The eight BEs for read-modify-write memory cycles are multiplexed on MEM_BE[3:0].

When not running a read-mod-write cycle MEM_BE[3:0] should indicate all data lanes are enabled—MEM_RMW_BE[7:0]# all asserted low.

MEM_DATA_OE# L14 U2.196 U3.145

O I

660 Memory Data Output Enable signal. When asserted, the 663 drives the MEM_DATA bus on the next CPU_CLK.

Section 2 — Signals

Table 2-9. InterChip Communication Signals (Continued) Signal Name MCM Nodes Description

660 Memory Error signal. When asserted, indicates an uncorrectable multi-bit or parity error has occurred during a memory read. This signal is only valid on the third CPU_CLK after MEM_RD_SMPL is asserted.

MEM_RD_SMPL J12 U2.49 U3.161

O I

660 Memory Read Sample signal. This signal is used by the ECC logic to determine when to sample ECC results. This signal is also used by the PCI read extension latch and the PCI-to-MEM read latch to load new data.

MEM_WRL_OPEN AC14 U2.51 U3.150

O I

660 Memory Write Latch Open signal. When asserted, the MEM write latch accepts new data on each CPU_CLK. When deasserted, the MEM write latch holds its current contents.

MWS_P2MRXS C30 U2.66

U3.152 O I

660 Memory write select/PCI-to-memory read crossover select signal.

When the memory write latch is sampling data, this signal controls the memory write multiplexer. Pull up with 10K (nominal) resistor to select (during reset) 603e in 3:2 core:bus clock mode.

PCI_AD_OE# N14 U2.195

U3.144 O I

660 PCI Data Output Enable signal. While asserted, the 663 drives the PCI_AD bus. Note: This is an asynchronous input to the 663.

PCI_EXT_SEL U14 U2.67 U3.153

O I

660 PCI Read Extension Select/PCI Write Extension Select signal.

When the PCI is reading from memory, this signal controls the PCI read extension multiplexer.

PCI_OL_OPEN W14 U2.64 U3.165

O I

660 PCI Other Latches Open signal. This signal controls the latch en-ables for the PCI-to-MEM read latch, the PCI read extension latch, and the PCI write extension latch.

PCI_OUT_SEL R14 U2.68 U3.169

O I

660 PCI Output Select signal. When asserted, memory data is routed to the PCI output bus, else CPU data is routed to the PCI output bus.

This signal is asynchronous.

ROM_LOAD U20 U2.70

U3.160 O I

660 ROM Load signal. This signal is used to load data from a ROM one byte at a time until eight bytes are received, then pass the eight bytes to the CPU.

663_SBE# G20 U2.193

U3.175 I O

660 SBE# Single-Bit Error signal. When asserted, indicates a correct-able single-bit error has occurred on the memory data bus. This signal is valid only on the CPU_CLK following the assertion of MEM_RD_SMPL. If the memory is not in ECC mode, this signal is unde-fined.