ROM Writes

ROM Data Byte ROM Address PCI_AD[23:0]

ROM Data PCI_AD[31:24]

CPU_DATA[0:63]

After Shift (BE Mode)

CPU_DATA[0:63]

After Shift (LE Mode)

1 Byte 0 XX XXX0h a — —

2 Byte 1 XX XXX1h b — —

3 Byte 2 XX XXX2h c — —

4 Byte 3 XX XXX3h d — —

5 Byte 4 XX XXX4h e — —

6 Byte 5 XX XXX5h f — —

7 Byte 6 XX XXX6h g — —

8 Byte 7 XX XXX7h h abcd efgh hgfe dcba

6.1.1.2 Address, Transfer Size, and Alignment

During ROM reads, system ROM is linear-mapped to CPU memory space from 4G – 2M to 4G (FFE0 0000h to FFFF FFFFh). This address range is translated onto PCI_AD[23:0]

as 0 to 2M (0000 0000h to 001F FFFFh). Since the CPU begins fetching instructions at FFF0 0100h after a reset, the most convenient way to use a 512K device as system ROM with the CPU is to use it from 4G – 512K to 4G. Connecting PCI_AD[18:0] to ROM_A[18:0]

with no translation implements this. With this connection, the system ROM is aligned with 4G – 2M, but with alias addresses every 512K up to 4G. Other size devices can also be implemented this way.

The CPU read address need not be aligned on an 8-byte boundary. A CPU read from any ROM address of any length that does not cross an 8–byte boundary, returns all eight bytes of that double-word from the ROM. For example, the operations shown in Table 6-1 could have been caused by a CPU memory read to FF80 0100h, FF80 0101h, or FF80 0105h.

6.1.1.3 Endian Mode Considerations

In little-endian mode, the address munging done by the CPU has no effect because PCI_AD[2:0] are forced to 000 during the address phase by the 660 at the beginning of the transaction. However, in little-endian mode the byte swapper is enabled, so the bytes of ROM data returned to the CPU are swapped as shown in the last column of Table 6-1.

6.1.1.4 4-Byte Reads

The 660 handles 4-byte ROM reads (and all ROM reads of less than 8 bytes) as if they were 8-byte reads. All 8 bytes are gathered by the 660, and all 8 bytes are driven onto the CPU data bus.

6.1.2 ROM Writes

The 660 decodes a CPU store word instruction to CPU address FFFF FFF0h as a ROM write cycle. (Note that the 660 treats any access from FFE0 0000h to FFFF FFFE, with

Section 6 — ROM

CPU_A[31]=0, as an access to FFFF FFF0.) The three low-order bytes of the CPU data word are driven onto the ROM address lines, and the high-order byte is driven onto the ROM data lines. For example, a store word instruction with data = 0012 3456h writes 56h to ROM location 00 1234h. Only single-beat, four-byte write transfers (store word) are sup-ported. A ROM write is considered to be a BCR operation. The ROM write BCR is detailed in Section 6.3.1.

The ROM write discussion assumes that the system is in big-endian mode. For the effects of little-endian mode operation on ROM reads, see Section 6.1.2.3. In direct-attach mode, the ROM is attached to the 660 as shown in Figure 6-3.

Figure 6-3. ROM Connections

ROM Address Data Control System 660

Bridge 60X

CPU

60X Bus

PCI_AD Lines

ROM_OE#, ROM_WE#

[23:0]

[31:24]

6.1.2.1 ROM Write Sequence

This case assumes that the PCI bus is parked on the CPU. Initially, the CPU drives the ad-dress and adad-dress attributes onto the CPU bus and asserts TS#. The 660 decodes the CPU transfer as a ROM write transaction, which is a BCR transaction.

The 660 initiates a BCR transaction by asserting PCI_FRAME# on the rising edge of PCI_CLK. Note that the 660 is driving PCI_AD[23:0] with the ROM address and PCI_AD[31:24] with the ROM data. On the next PCI_CLK, the 660 negates PCI_FRAME#

and asserts IRDY#. Four PCI_CLKs after the 660 asserts PCI_FRAME#, it asserts ROM_WE# for two PCI_CLKs.

The 660 completes the PCI transaction by deasserting PCI_IRDY#. The 660 signals TA#

and AACK# to the CPU to signal transfer completion to the CPU. Also note that PCI_DEV-SEL#, PCI_TRDY#, PCI_STOP#, and ROM_OE# are negated throughout the transaction.

6.1.2.2 Write Protection

Write protection for direct-attach ROM is provided through the ROM lockout BCR (see Sec-tion 6.3.2). ROM write-lockout operaSec-tions are compatible with the 650 bridge.

When a CPU busmaster writes any data to memory address FFFF FFF1h, the 660 locks out all subsequent ROM writes until the 660 is reset. In addition, flash ROM devices can have the means to permanently lock out sectors by writing control sequences. Flash ROM specifications contain details. Note that the 660 treats any access from FFE0 0001 to FFFF FFFF, with CPU_A[31]=1, as an access to FFFF FFF1.

6.1.2.3 Data Flow In Little-Endian Mode

Figure 6-4 and Table 6-2 show the flow of CPU Data through the 660 to the ROM while the system is in little-endian mode. Note that the CPU Data bus is labeled in big-endian order, the PCI bus is labeled in little-endian order, and the 660 is labeled to match (and the bit significance within the bytes is maintained).

Figure 6-4. ROM Data and Address Flow In Little Endian Mode

When the CPU executes a store word instruction to FFFF FFF0h, the contents of the source register appear on CPU_DATA[32:63]. CPU_ADDR[29] is 1 (after the CPU munges the ad-dress), so the 660 selects CPU data byte lanes 4 through 7 as the source of the data. The system is in little-endian mode, so the buffer swaps the data bytes. If the register data is AB012345h, then ABh is written to address 012345h of the ROM. Only single-beat, four-byte write transfers (store word) are supported.

Table 6-2. ROM Write Data Flow in Little-Endian Mode

CPU Register CPU DATA[0:63] Content PCI_AD[31:0] ROM Signal

MSB 32:39 ROM Data 31:24 D[7:0]

40:47 ROM Address high byte 23:16 A[23:16]

48:55 ROM Address mid byte 15:8 A[15:8]

LSB 56:63 ROM Address low byte 7:0 A[7:0]

6.1.2.4 Data Flow In Big-Endian Mode

Figure 6-5 and Table 6-3 show the flow of CPU Data through the 660 to the ROM while the system is in big-endian mode. Note that the CPU Data bus is labeled in big-endian order, the PCI bus is labeled in little-endian order, and the 660 is labeled to match (and the bit significance within the bytes is maintained).

Section 6 — ROM

Figure 6-5. ROM Data and Address Flow In Big Endian Mode 60X CPU

When the CPU executes a store word instruction to FFFF FFF0h, the contents of the source register appear on CPU_DATA[0:31]. CPU_ADDR[29]=0, so the 660 selects CPU data byte lanes 0 through 3 as the source of the data. The system is in big-endian mode, so the buffer does not swap the data bytes. If the register data is 452301ABh, then ABh is written to address 012345h of the ROM. Only single-beat, four-byte write transfers (store word) are supported.

Table 6-3. ROM Write Data Flow in Big-Endian Mode

CPU Register CPU DATA[0:63] Content PCI_AD[31:0] ROM Signal

MSB 0:7 ROM Address low byte 7:0 A[7:0]

8:15 ROM Address mid byte 15:8 A[15:8]

16:23 ROM Address high byte 23:16 A[23:16]

LSB 24:31 ROM Data 31:24 D[7:0]