Other L2 Related BCRs See Table 3-6

Table 3-6. Other L2 Related BCRs

Bridge Control Register Index R/W Bytes

Error Enable 2 Index C4 R/W 1

Error Status 2 Index C5 R/W 1

Bridge Chip Set Options 3 Index D4 R/W 1

System Control 81C 8000 081C R/W 1

L2 Invalidate 8000 0814 R

L2 Error Status 8000 0842 R

L2 Parity Error Read and Clear 8000 0843 R

Cache Status Index B1h R/W

Figure 3-4. L2 Mapping of System Memory – 512K Configuration

The L2 considers the 1G of cacheable system memory to be logically organized into 4K pages. Every member of a given page has the same address tag, which in this case is defined as bits A[2:13] of the address.

Each page consists of 8K blocks of memory, where each block consists of one 32-byte doubleword of memory. A block is referred to within the page by the index, which is defined as bits A[14:26] of the address.

Thus each block of memory in the 0 to 1G range has a tag, A[2:13], which ranges from 0 to 4K–1, and an index, A[14:26], which ranges from 0 to 8K–1. All of the blocks that have the same index are said to be in the same congruence class, or set. Each block in a given set has a unique tag. Some map-ping examples:

Figure 3-5 shows how the MCM maps the SRAM to main memory using the index and tag fields of the address. Notice that there are 8k tags and 8k 32-byte blocks in the SRAM, and that the main memory is divided up into 4k pages, each one of which is composed of 8k blocks.

When an address is presented to the cache directory for snooping, the MCM uses the index to select which directory location to access, by presenting A[14:26] to the tagRAM address inputs. The tagRAM then compares the tag in that location (the A[2:13] of the previous cacheable access to that location) to the tag ( A[2:13] ) of the current transaction. If there is a match, and the tag is marked ”valid,” then there is a cache hit (signalled by TAG_MATCH).

Section 3 — CPU & L2

Figure 3-5. SLC L2 Cache Directory – 512K Configuration 0

Suppose the CPU requests a burst store to location 512K (8 0000h), which is initially invalid (either stale or never accessed). The index is A[14:26], which is 0h, so the accessed ta-gRAM location is 0h. The tag currently on the address bus is A[2:13], which equals 2. So the MCM stores 2h into tagRAM location 0h. The valid bit is set for that location.

While the CPU is accessing other blocks of memory with different low order addresses, oth-er locations in the tagRAM are being accessed; howevoth-er, if the CPU again accesses a block of memory with this same low order address, then this tagRAM location will again be ac-cessed, and the tag stored therein will be compared against A[2:13] of the current access.

If they are the same, then there is a cache hit.

3.7.6 SRAM

The MCM uses four IBM041814 synchronous 64K x 18 SRAMs to implement the SRAM portion of the L2. Figure 3-6 shows the basic connectivity of the MCM SRAM. These are synchronous devices, and each SRAM consumes one of the MPC970 clocks. In burst op-eration, the address of the data for the initial beat of the burst is latched into the SRAM; the address of the data for the next beat of the burst is incremented internally under the control of the ADV# input (SRAM_CNT_EN#).

S Each SRAM is connected to two CPU bus data bytes and the associated two CPU bus parity lines.

S ABUF[13:28] are a buffered copy of CPU A[13:28]. The SRAMs are arranged in par-allel, so that an 8-byte doubleword is addressed during each access; thus, ABUF[28] is connected to A0 of the SRAM.

S The 660 asserts SRAM_WE# to write into the SRAM and asserts SRAM_OE# to read data out of the SRAM.

S The 660 asserts SRAM_ADS# to signal the initial beat of the burst.

S Pull SRAM_CS# low for normal operation. Pull SRAM_ADSP# high for normal op-eration.

Figure 3-6. Synchronous SRAM, 512K L2 CS

Address SRAM

D[0:15] D[16:31] D[32:47] D[48:63]

DP[0:1] DP[2:3] DP[4:5] DP[6:7]

DQ DQ DQ DQ

ADV ADSC ADSP

OE WE A[13:28]

SRAM_CNT_EN#

SRAM_ADS#

SRAM_ADSP#

SRAM_WE#

SRAM_CS#

SRAM_OE#

U7 U8 U9 U10

SRAM_BCLKs

0 1 2 3

SRAM SRAM

SRAM 32k x 18

SRAMs

3.7.7 TagRAM

The MCM uses an IDT71216 synchronous 16K x 15 cache tagRAM to implement the tags of the L2. Figure 3-7 shows the basic connectivity of the MCM SRAM. The tagRAM is a synchronous device, and so consumes one of the MPC970 clocks.

S CPU address lines A[14:26] form the index of the directory entry. Pull TAG_ADDR_13 high for normal operation.

S CPU address lines A[2:13] form the tag of the directory entry. Tie TAG_DATA_11 to A13 for normal operation.

S During tagRAM writes, the valid bit associated with the index is set to match the TAG_VALID input.

S During tagRAM reads, the TAG_MATCH output is released to the active high (open–

drain) state only when A[2:13] matches the contents of tagRAM location A[14:26], and the Valid bit for that location is set to 1. If the the Valid bit is 0 (invalid) or the address stored in the tag does not match the current value of A[2:13], then the TAG_MATCH output is driven low.

Figure 3-7. Synchronous TagRAM, 512K L2 CS

VALID

MATCH TAG_MATCH

16k x 15 TagRAM

V_DD X_TAG_BCLK

TAG_VALID A[14:26]

TAG_CLEAR TAG_WE A[12:0]

TAG[11:0]

A[2:13]

TAG_CLEAR#

TAG_WE#

Section 4 — DRAM

Section 4 DRAM

The memory controller in the 660 bridge controls the system memory DRAM. The system memory can be accessed from both the CPU bus and the PCI bus. Much of the information in this section has been drawn from the 660 User’s Manual.