turned off, disabling almost of all system functions.
In either of the standby modes, the output ports, internal registers and internal RAMs are allowed to retain their contents.
Transition from operation mode to a standby mode
Table 11 Comparison Between of Halt and Stop Modes
DIFFERENCE HALT MODE STOP MODE
Functions that do not require system Functions that do not require external
standby mode IF corresponding to standby release
Registers IE and IF are reset.
Standby release events 9 (including reset) 7 (including reset)
en
a:
HALT MODE
Execution of the halt instruction puts the SM831 x into the halt mode and the system clock is turned off, stopping the current program. Since the main clock oscillator connected across CK1 and CK2 pins is active during the halt mode, devices requiring no system clock are kept in-operation. These devices are serial II0s and timers.
The halt mode is disabled by one of the following means and the program will start again.
• Release by reset input
A Low level on the RESET pin will cause the SM831 x to exit halt mode and start program at address OOOOH, the same way as with normal resetting.
• Release by interrupt
When an interrupt event occurs, the SM831 x exits the halt mode.
When a bit in the enable flag IE is set, the SM831x exits the halt mode if the interrupt request corresponding to the bit is generated. The action of the SM831 x after exiting the halt mode is determined by the setting of the IME flag.
• IME
=
0The program will start at the location following the halt instruction address. Note that the bit in the interrupt flag register IF that caused the previous interrupt is kept set.
• IME
=
1After returning from the halt mode, the program will start at the vectored address. This is the same as with the normal interrupt handling process.
STOP MODE
Executing the STOP instruction puts the SM831 x to the stop mode and turns off the main clock and system clock. All operations stop. Exception are serial I10s, timers operating on external clock and clock generated across pins OSON and OSCOUT.
The stop mode is canceled by the following factors and the program starts after the specified time (return time).
• Reset input
A Low level on the RESET pin will cause the SM831 x to exit the stop mode and start program at address OOOOH, quite the same as with normal resetting. For detailed description of reset, refer to
"Hardware Reset Function"
• Interrupt request
While operating on the external clock or clock generated across pins OSCIN and OSCOUT, an interrupt from a serial 110, timer, or external input pin KI or KH causes the program to continue at the address following the STOP instruction.
• Stop release register STPR
(STPR, FFFDH, R/w)
Bit 7 6 5 4 3 2 1 0
STPR
I - ISR61 - ISR41sR31sR21sR11sRO I
The stop release register STPR determines interrupts that are used to release the stop mode.
This register will not be effective during the halt mode. There are 6-interrupt sources for releasing the stop mode.
Table 12 Stop Mode Release Bits
STPR BIT STOP MODE RELEASE EVENT 1 : Enable
o :
DisableSRO Low level input from KI pin (generation of interrupt request Signal IROO) SR1 Timer 0 overflow (generation of interrupt request signal IR01)
SR2 Timer 1 overflow (generation of interrupt request signal IR02) SR3 Timer 2 overflow (generation of interrupt request signal IR03)
SR4 Interrupt request from KH pin (P67) (generation of interrupt request signal IR04)
-SR6 Interrupt request upon end of serial liD (generation of interrupt request signal IR06)
-Interrupt
The SM831x is designed to accommodate 9-independent maskable interrupt (7 -internal and 2-external) which can be assigned to 9-interrupt
vector address.
One nonmaskable interrupt is available with the SM831x for use with a watch dog timer.
Interrupt enable register IE
IROO
IR01
IR02
IR03
Interrupt vector address generation
Interrupt master enable flag
INT
IR04 , - - - -___ NMI
IR05
IR06
IRQ7
Interrupt flag register IF
Reset signal
NMI---4--~
Nonmaskable interrupt (upon overflow of watch dog timer WDT)
Fig. 7 Interrupt Control Block
en a:
....
w=> a. :E
o u o a: u :lE
a.
X u uJ
...J
"
Zen ....
iD cO
INTERRUPT PRIORITY AND VECTOR ADDRESS
PRIORITY LEVEL ADDRESS INTERRUPT EVENT MASKABLE
1 0080 NMI : nonmaskable interrupt; Overflow of watch dog timer No 2 0040 IROO : External interrupt (KI) or zero cross detect input Yes
3 0048 IR01 : Timer
a
overflow interrupt Yes4 0050 IR02 : Timer 1 overflow interrupt Yes
5 0058 IR03 : Timer 2 overflow interrupt Yes
6 0060 IR04 : External interrupt (P67/KH) Yes
7 0068 IR05 : Timer 3 overflow interrupt or end of pulse width measurement (P46) Yes 8 0070 IRQ6 : Serial interface
9 0078 IR07 : End of AID conversion INTERRUPT FLAGS, REGISTER
• Interrupt master enable flag IME
This register is used to enable or disable all the maskable interrupts simultaneously.
Executing the EI instruction sets the master enable flag IME, enabling the maskable interrupts.
Executing 01 instruction resets the IME, disabling the maskable interrupts.
STATE OF IME FLAG INTERRUPT
1 Enable
0 Disable
• Interrupt flag register IF
(IF, FFFEH, R/w)
Bit ? 6 5 4 3 2 1 0
IF I IF? IIF6 IIF5 IIF4 IIF3 IIF2 IIF1 liFO I When interrupt event (IRQO to IRQ?) occurs, corresponding bit (IFO to IF?) in the interrupt flag register IF is set to "1 ". At the end of the interrupt process, the bit in the interrupt flag register IF is automatically clear. If the interrupt event is left unprocessed, the bit remains "1" until it is forced to clear by a program.
Yes Yes
• Interrupt enable register IE
(IE, FFFFH, R/w)
Bit ? 6 5 4 3 2 1 0
IE liE? IIE6 IIE5 IIE4 IIE3 IIE2 IIE1 I lEO I This register is used to individually enable or disable 9-maskable interrupt. Setting a bit in this register to "1" enables corresponding interrupt; and
"0" disables the interrupt. The setting of the interrupt enable register is made effective when the interrupt master enable flag IME is set.
The I E register also sets the halt mode release conditions.
STATE OF
REGISTER IE BIT INTERRUPT
1 Enable (as well as halt mode release enable)
a
Disable (as well as halt mode release disable)MASKABLEINTERRUPTS
Maskable interrupts are selectively enabled or disabled. When a maskable interrupt occurs, it sets the corresponding bits in the flag register IF to 1 level. If the following 2 conditions are met, the microcomputer processes the interrupt, starting with the cycle following the end of the execution of the current instruction sequence.
• Interrupt master enable flag IME is set.
• Corresponding interrupt enable register IE bit is set at 1 level.
IF the above conditions are not met, the interrupt flag register IF bit remains 1 level. Setting flag IME and IE bit forces the microcomputer to immediately start the interrupt processing.
• Simultaneous interrupts
In the flag register IF, the bits corresponding to the interrupts are set to 1 level. The interrupt having the highest priority only is accepted.
Other interrupt(s) is suspended until one of the following conditions is satisfied.
• Upon finishing the current interrupt processing, RET1 instruction is executed to return to the main routine and to set the master enable flag IME to "1" again. This starts the processing of a suspended interrupt.
• Master enable flag IME is set to "1". And a suspended interrupt is processed. Because two interrupts are simultaneously processed, 2 more stack stages are used.
NON·MASKABLE INTERRUPT NMI
Non-maskable interrupt (NMI) is an interrupt which cannot be masked by a program. The return from the non-maskable interrupt routine.
When the control returns to the main routine, the interrupt master enable flag IME returns to the condition that was maintained before accepting the non-maskable interrupt provided that the neither EI nor 01 has been executed in the non-maskable interrupt routine.
If EI or 01 instruction has been executed during the non-maskable interrupt routine, the interrupt master enable flag IME is unchanged. If the EI instruction is executed during the non-maskable interrupt routine, the IME flag will be set upon returning to the main routine. If the 01 instruction is executed during the non-maskable interrupt routine, the IME flag will be clear.
The SM831 x will follow the normal reset sequence when returning from non-maskable interrupt routine when a reset signal is entered, resetting all flags and registers associated with that interrupt, ignoring all processes made to them.