Fig. 1 shows the SMS5CPU register lineup. The CPU internal register consists of eight S-bit general purpose registers (RO-R?), four 16bit general purpose registers
RRO four 16-bit general purpose registers (RRS-RR14).)
A1 GENERAL PURPOSE REGISTER
The eight S-bit general purpose registers RO-R? and all eight 16-bit general purpose registers (RRO-RR14) are available for use as accumulator, index register and pointer registers. (The RO and RRO cannot be used as index register)
The other eight S-bit registers RS-R15 cannot be used as S-bit general purpose register.
The feature of the SMS500CPU architecture is that general purpose registers are virtually allocated at 16-byte internal RAM. Actually, if the CPU accesses general purpose registers, the designated RAM will be accessed by the S-bit register pointer
Although the general purpose registers are members of the register file, which stores the data onto actual RAM, is different from the other members (control registers).
That is, general purpose registers can be referred as registers, as register file (allocated at OOOOH-OOOFH) and as RAM accessing by all addressing modes.
*
About register pointer _ (RP), please refer to [processor status (PSO)].en a:
CPU CONTROL REGISTER
The SM8500CPU has the following control register:
processor status PSO, processor status PS1, system configuration register SYS,stack pointer SPH, SPL and program counter PC. All control register except the program counter PC are members of the register file and accessible by the register file R and the register file pair RR addressing modes.
Processor status 0 (PSO)
The processor status PSO is an 8-bit readable/
writable register containing 2 fields, the upper 8-bit is register pointer (RP) and the lower 8-bit is interrupt mask.
Bit 7 0
I PR41 PR31 PR21 PR1 I PRO 11M2 IIM1 IIM1 I
Bit 7-3 : Register pointer (RP)
This gives, in 8 bytes unit, the starting address in RAM for general purpose registers.
I \
PSO
I
R PI
1MI
Bit 2-0 : Interrupt mask bit (1M) BIT
000
r---oo1
010 011 100 101 111 111
RO R1
R14 R15
CONTENT
All maskable interrupts recognized
Maskable interrupts with level 1 to 12 recognized Maskable interrupts with level 1 to 10 recognized Maskable interrupts with level 1 to 8 recognized Maskable interrupts with level 1 to 6 recognized Maskable interrupts with level 1 tto 4 recognized Maskable interrupts with level 1 to 2 recognized
Address Low
Ex.) If RP=OOOOOB, general purpose registers will be virtually allocated at internal RAM OOOOH-OOOFH.
High
If RP=00001 B,general purpose registers will be virtually allocated at internal RAM OOOSH-0017H.
Internal RAM
Processor status 1 (PS1)
The processor status PS 1 is an 8-bit readable/
writable register and consists of eight flag bits.
These flags can be use as the condition codes for the conditional branch instructions. When CPU generates an interrupt, the content of processor status PS1 and the value of program counter PC automatically are pushed onto stack.
Bit 7 0
It indicates that the last arithmetic operation was a subtract.
System configuration register (SVS)
The system configuration register SYS is an 8-bit readable / writable register which sets the external memory expansion modes and selects 8-bit / 16-bit
Bit 2-0 : Memory configuration (MCNF2-0)
BIT CONTENT
000 External memory expansion disable.
011 External memory expansion (256 bytes, FFOOH-FFFFH)
External memory expansion mode 110 (64k bytes *) memory access field is BOOOH-FFFFH.
Stack pointer (SPL, SPH)
The stack pointer SPL, SPH are 8-bit readable/
Program counter (PC)
The program counter (PC) is a pointer for program memory and contains the starting address for the next instruction.
Bit 15
o
I I I I
The program counter PC is initialized to 1020H after hardware reset. That is, the application program starts executing from the address 1020H after hardware reset.
Memory configuration register (MCF) only use in SM8505!SM8506
This is a register which sets the accessible address range of internal memory within internal ROM field (1000H-FFFFH). The outside field which set by this register can be used as the access field of external memory. Had set this register as soon as the setting memory field becomes valid. The internal memory beyond the setting field cannot be
Bit 7 0
C
I - I - I - I MC31 MC21 MC1 I Mca IBit 3-0 : Build-in memory accessing field selection bit BIT BUILD-IN MEMORY ACCESSING FIELD
accessed. To access the external memory, it is necessary to switch the SM8505!SM8506 to external memory expansion mode by setting the bits MCNF2-MCNFO (bit 2-0 : SYS). The initial value of the register is in the all build-in ROM accessible state. This register is only valid for SM8505!SM8506.
For all others SM8500 series, other than SM8505!
SM8506, the operation for the register read/write does not affect to microcomputer internal action.
Internal! external overlap memory field is accessible by program switching. While the program switches to access internal memory from external memory, only if sets the external memory expansion mode to be invalid by setting system configuration register SYS, the overlap internal memory is impossible to access.
The access field also is necessary to change by register MCF. In addition, if sets the bits MC3-MCO to '0000' and the corresponding pins is in the state, same as external memory expansion mode, then all internal ROM will be accessible.
EXTERNAL MEMORY FIELD
0000 60k bytes 1000H-FFFFH Nothing
0001 56k bytes .1000H-EFFFH 4k bytes FOOOH-FFFFH
0010 52k bytes 1000H-DFFFH 8k bytes EOOOH-FFFFH
0011 48k bytes 1000H-CFFFH 12k bytes DOOOH-FFFFH
0100 44k bytes 1000H-BFFFH 16k bytes COOOH-FFFFH
0101 40k bytes 1000H-AFFFH 20k bytes BOOOH-FFFFH
0110 36k bytes 1000H-9FFFH 24k bytes AOOOH-FFFFH
0111 32k bytes 1000H-8FFFH 28k bytes 9000H-FFFFH
1000 28k bytes 1000H-7FFFH 32k bytes 8000H-FFFFH
1001 24k bytes 1000H-6FFFH 36k bytes 7000H-FFFFH
1010 20k bytes 1000H-5FFFH 40k bytes 6000H-FFFFH
1011 16k bytes 1000H-4FFFH 44k bytes 5000H-FFFFH
1100 12k bytes 1000H-3FFFH 48k bytes 4000H-FFFFH