The SM8500 supports 16 interrupt sources.
In these interrupts, watchdog timer and illegal instruction trap interrupts are belong to non-maskable interrupt, the others, however, are maskable interrupts
16 interrupt sources are shared to independent interrupt vector, respectively, in the ROM address area between 1 000H-1 01 FH. And, the maskable interrupts are set to 14 steps with priority level.
PSO Interrupt flag register Interrupt enable register IFO
IF1 PS1
with priority 14 level 0
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Illegal Instruction trap ---=>:=;;. Interrupt process Fig. 10 Interrupt block diagram
Table 3 SM8500 interrupt vectors location and their priority
VECTOR LOCATION INTERRUPT SOURCE SYMBOL PRIORITY*
1000H External pin input (P33/PINTo/CINTo) PINTO 1
1002H External pin input (P36/PINT1) PINT1 2
1004H Timer (TIMO) match signal TIMOINT 3
1006H Timer (TIM1) match signal TIM11NT 4
1008H UART transmiVreceive complete UARTINT S
100AH SIO transmiVreceive complete SIOINT 6
100CH Timer (TIM2) match signal TIM21NT 7
100EH Timer (TIM3) match signal TIM31NT 8
1010H Timer (TIM4) match signal TIM41NT 9
1012H Timer (TIMS) match signal TIMSINT 10
1014H Clock Timer (TIM6) overflow TIM61NT 11
1016H AID converter complete ADINT 12
1018H External pin input (P3?/PINT2) PINT2 13
101AH External pin input (pOo-PO?) KYINT 14
101CH Watchdog timer overflow WDTINT
-101 EH Illegal instruction IRRINT
-*
The priority levels determine the order in which the chip process simultaneous interrupts. It also denotes the priority level of mask interrupts by setting the bits IM2-IMO (bit 2-0 : PSO).Register Explanations
interrupt mask bit (1M) of processor status 0 (PSO)
The bits IM2-IMO can set the acceptable level for interrupt. The maskable interrupt requested by CPU is set to 1 to 14 priority level. These bits IM2-IMO determine processing interrupts which priority level.
Bit 2-0 : Interrupt mask bit (IM2-IMO)
BIT CONTENT
000 All maskable interrupts recognized.
001 All maskable interrupts recognized.
Maskable interrupts with 1 to 12 level 010 recognized.
Maskable interrupts with 1 011 recognized.
to 10 level
100 Maskable interrupts recognized.
with 1 to 8 level Maskable interrupts with 1 to 6 level 101 recognized.
110 Maskable interrupts recognized.
with 1 to 4 level Maskable interrupts with 1 to 2 level 111 recognized.
* When an Interrupt enables by Interrupt mask bit, If all interrupt conditions are setup, then the CPU starts to the interrupt processing.
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Interrupt enable bit (I) of processor status 1 (PS1)
The bit I (bit 0 : PS1) enables/disables all maskable interrupts. After hardware reset, the bit I is cleared to '0' and so all maskable interrupts are in disable state.
Bit 0 : Interrupt enable (I).
BIT CONTENT
0 Disable to accept all maskable interrupts Enable to accept maskable interrupt. For 1 each maskable interrupt can be enabled/
disabled by interrupt enable register lEO, IE1 and bits IM2-IMO.
Except that write to processor status PS1 directly, the bit I can be seVcleared by the following special-purpose instructions. (Under normal case, the special-purpose instructions are used.)
DI instruction: bit I is cleared to '0'.
EI instruction: bit I is set to '1 '.
Interrupt enable register
a
(lEO)The interrupt enable register I EO is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources.
Bit 7 0
IIED711ED611EDSIIED411ED311ED211ED1 IIEDD I
Bit 7 : PINTO Interrupt Enable bit Bit 6 : PINT1 Interrupt Enable bit Bit 5 : Timer 0 Interrupt Enable bit Bit 4 : Timer 1 Interrupt Enable bit Bit 3 : UART Interrupt Enable bit Bit 2 : 810 Interrupt Enable bit Bit 1 : Timer 2 Interrupt Enable bit Bit 0 : Timer 3 Interrupt Enable bit
BIT CONTENT
0 disable 1 enable
Interrupt enable register 1 (IE1)
The interrupt enable register IE1 is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources.
Bit 7 0
IIE1711E1611E1SIIE1411E1311E121 - I - I
Bit 7 : Timer 4 Interrupt Enable bit Bit 6 : Timer 5 Interrupt Enable bit Bit 5 : Timer 6 Interrupt Enable bit Bit 4 : AID Interrupt Enable bit Bit 3 : PINT2 Interrupt Enable bit Bit 2 : PO Interrupt Enable bit
BIT CONTENT
0 disable 1 enable
The bit 1 and bit 0 are readable/writable bits. To manipulate these bits also do not affect others operation of the microcomputer.
The interrupt enable register lEO and IE1 also are used to wake up the chip from standby mode (STOP mode, HALT mode) by setting the interrupt to snable. If the interrupt enabled by the interrupt enable register lEO and IE1 occurs, the chip will wake up from standby mode. But also there is interrupt source which cannot use to wake up from STOP mode.
Interrupt flag register
a
(IFO)The interrupt flag register IFO is an 8-bit readable/
writable register. If the interrupt occurs, the corresponding bit will be set to '1 '.
Bit 7 0
IIFO?IIF061IF051IF041IF031IF021IF01 IIFOO I
Bit 7 : PINTO Interrupt Request bit Bit 6 : PINT1 Interrupt Request bit Bit 5 : Timer 0 Interrupt Request bit Bit 4 : Timer 1 Interrupt Request bit Bit 3 : UART Interrupt Request bit Bit 2 : SIO Interrupt Request bit Bit 1 : Timer 2 Interrupt Request bit Bit 0 : Timer 3 Interrupt Request bit
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1_ CONTENT1 request
Interrupt flag register 1 (IF1)
The interrupt flag register I FO is an 8-bit readable/
writable register. If the interrupt occurs, the corresponding bit will be set to '1 '.
Bit 7 0
IIF1?IIF16'IF15'IF14'IF13'IF12' - , - I
Bit 7 : Timer 4 Interrupt Request bit Bit 6 : Timer 5 Interrupt Request bit Bit 5 : Timer 6 Interrupt Request bit Bit 4 : AID Interrupt Request bit Bit 3 : PINT2 Interrupt Request bit Bit 2 : PO Interrupt Request bit
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CONTENTPO control register (POC)
The control register POC is an 8-bit readable/
writable register and enables/disables the external interrupt POO-PO? in bit unit.
The external internal POO-PO? occurs with falling edge of each input pin and is shared to same interrupt vector (101 AH-1 01 BH). The bit IE12 (bit 2 : IE1) can disable all the external internal POO-PO? .
Bit 7 0
'pac?' POC6' POC5' POC4' POC31 POC21 POC11 pocol Bit 7 : PO? Interrupt Enable bit
Bit 6 : POs Interrupt Enable bit Bit 5 : POs Interrupt Enable bit Bit 4 : P04 Interrupt Enable bit Bit 3 : P03 Interrupt Enable bit Bit 2 : P02 Interrupt Enable bit Bit 1 : P01 Interrupt Enable bit Bit 0 : POo Interrupt Enable bit
BIT CONTENT
0 enable 1 disable
External interrupt mode register (EXIN)
The register is use for setting external interrupt ports (PINTO/P33, PINT1/P3s, PINT2/P3?).
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Interrupt Control Register Interrupt Source
Mask Enable Priority Level Enable Register Other
External pin input (P33/PINTo/CNTo) lEO? (bit? : lEO) EXSOO-01 (bit?-6 : EXIN) (Sampling clock selection)
(including capture input) EXOO-01 (bitS-4 : EXIN) (Detect edge selection)
External pin input ( P36/PINT1) IE06 (bit6 : lEO) EX10-11 (bit3-2 : EXIN)
(Low level detect, detect edge selection)
Timer (TIMO) match signal IEOS (bitS: lEO) , ' ... .
Timer (TIM1) match signal IE04 (bit4 : lEO)
UART transmit/receive complete IE03 (bit3 : lEO)
SIO transmit/receive complete IE02 (bit2 : lEO) .
Timer (TIM2) match signal IE01 (bit1 : lEO)
Timer (TIM3) match signal IEOO (bitO : lEO)
Timer (TIM4) match signal Bit 1 Bit 1M IE1? (bit? : IE1)
Timer (TIMS) match signal (bitO:PS1) (bit2-0:PSO) IE16 (bit6: IE1)
Clock Timer (TIM6) overflow IE1S (bitS: IE1)
AID converter complete IE14 (bit4: IE1)
External pin input (P37/PINT 2) IE13 (bit3 : IE1) EX20-21 (bit1-0 : EXIN)
(Low level detect, detect edge selection)
External pin input (PO) ---- -P07 -- --- IE12 (bit2 : IE1) ~~~?_ (~i!~ _:_~~~) _~~? J:i~_~~~~~~! ?j~~~~~ __________
P06 (All of PO pins enable I disable) ~~~~_ (~i!~ _: _~~~) _~~~ J:i~ _ ~~~~~~! _dj~~~~~ __________
---P05 ~~~?_ (~i!~ _:_~~~) _~~~J:i~_~~~~~~! ?j~~~~~ __________
---P04 _~~~~_ ~~i!~ _: _~g~) _~~1 J:i~ _ ~~~~!~! _dj~~~!~ __________
----- -
----P03 ~~~~_ ~~i!~ _:_~g~) _~~~?i~_~~~~!~! ?j~~~!~ __________
---P02 ~~~_2_ ~~i!~ _: _~g~) _~~??i~_ ~~~~!~! _dj~~~!~ __________
---P01 _~~~_1_ ~~i!! _:_~~~) _~~l Ri~_ ~~~~~~! _d_i~~~~~ ___________
---POo POCO (bitO : POC) POo pin enable I disable
Watchdog timer overflow WOTRN (bit6:WOTC) select the operation as an interrupt occurs
Illegal instruction trap - ----~-- ~~-~--~.~-~.~. '---~ ....
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