Clock System - GENERAL INFORMATION II

The SM8500 uses the main-clock and sub-clock oscillator circuits to generate the required clock.

fcK=11.0592MHz

---CK_1N Main-Clock generator circuit

The system clock, lead CPU operation, is one of the five clocks which dividing the main-clock (fcK) into 1/2, 1/4, 1/8, 1/16, 1/32. It also selects from sUb-clock (f32K). In addition, the clocks supplied to the peripheral functions are fCl-fc1O divided by the prescaler PRSO and derived from the 112 clock of main-clock, (fcK/2). It is also are fXl-fxa divided by the prescaler PRS1 and derived from the sub-clock.

System clock

SM85 CPU

Function Blocks RAM register

OSC_1N OSC_OUT

Sub-Clock generator circuit

Operation read / write

Interrupt Control Peripheral Functions

Fig. 7 SM8500 clock system

System Clock frequency control

System clock fSYS

M~~n:c_lo_Ck ^__---+<f ... ·~1

_ · · · _ · · _ · · 1

Fig. 8 SM8500 clock system (equivalent circuit for clock system peripheral blocks) Clock change register (CKKC)

Clock change register CKKC is an 8-bit readable/

writable register containing the control of system clock change and the setting of warming up period after waking up from the STOP mode.

Clock change register CKKC is initialized to OOH after hardware reset.

Bit 7

o

Bit 7 : Clock change enable bit (FCPUEN)

o I

disable system clock speed change 1

I

enable system clock speed change Bit 6 : Main-clock stopped bit (MCKSTP)

Main-clock stopped allows switching to sub-clock used as system clock.

BIT SYSTEM CLOCK FREQUENCY

000 system clock

=

(1/32) x main-clock produces unrealiable operation.

Bit 1-0 : Warming up selection bit (WUPS1-WUPS1 0)

"T1

Address Space Register File

OOOOH

rg. physically present

~ Area

~ Interrupt Vector

rg. ~ _o· ^Area

001 BH Control register 001 CH Stack Pointer SPH The address for others models in 5MB500 series listed below

5MB502 5MB503 5MB504 5MB505 5MB506

" ^03FFH ^03FFH ^03FFH ^07FFH ^07FFH

Timer (TIM4) match signal •• t~ee~rJ.

(TIM4INT) (Lower)

Timer (TIM5) match signal.J~ee~rJ.

(TIM4INT) . (Lower)

Clock Time (TIM6) overfJo'U. t~ee~rJ.

(TIM6INT) . (Lower)

ND converter complete .••• {~ee~rJ.

(ADINT) (Lower)

External pin input (Upper)

(PINT2) .. _-^(C;;~;)·

External pin input ·---f(ee~rJ.

(POO-P07) Lower)

Watchdog Timer interrupt __ t~ee~rJ.

(WDTINT) (Lower)

(X)

Address Register name RIW Initial value Address Register name OOOOH General purpose register RO RRO RIW Undefined 0020H PO (Input) register

0001H General purpose register R1 RIW Undefined 0021H P1 (Input/Output) register 0002H General purpose register R2 RR2 RIW Undefined 0022H P2 (Input/Output) register 0003H General purpose register R3 RIW Undefined 0023H P3 (Input/Output) register 0004H General purpose register R4 RR4 RIW Undefined 0024H P4 (Input) register 0005H General purpose register R5 RIW Undefined 0025H P5 (Input/Output) register 0006H General purpose register R6 RR6 RIW Undefined 0026H P6 (Output) register 0007H General purpose register R7 RIW Undefined 0027H P7 (Input/Output) register 0008H General purpose register R8 RR8 RIW Undefined 0028H P8 (Input/Output) register 0009H General purpose register R9 RIW Undefined 0029H P9 (Input/Output) register OOOAH General purpose register R10 RR10 RIW Undefined 002AH PA (Output) register OOOBH General purpose register R11 R!W Undefined 002BH UART Transmit data register OOOCH General purpose register R12 RR12 RIW Undefined 002CH UART Receive data register OOODH General purpose register R13 RIW Undefined 002DH UART Status register OOOEH General purpose register R14 RR14 RIW Undefined 002EH UART Control register OOOFH General purpose register R15 RIW Undefined 002FH UART Baud rate setting register 0010H Interrupt enable register 0 lEO RIW OOH 0030H PO Control register

0011H Interrupt enable register 1 IE1 RIW OOH 0031H P1 Control registe 0012H Interrupt flag register 0 IFO RIW OOH 0032H P2 Control registe 0013H Interrupt flag register 1 IF1 RIW 03H 0033H P3 Control registe 0014H External interrupt mode register EXIN RIW OOH 0034H P4 Control registe 0015H SIO Control register SRC RIW OOH 0035H P1 Pull-up setting register 0016H SIO Data register SRD RIW Undefined 0036H P2 Pull-up setting register 0017H AJD Data register ADCD RIW OOH 0037H P7 Control registe 0018H AJD Control register ADCC RIW OOH 0038H P8 Control registe 0019H System configuration register SYS RIW *0000000 0039H P9 Control registe 001AH Clock change regsiter CKKC RIW OOH 003AH P5 Control registe 001BH Reverse (access disable) 003BH Port Pull-up setting register

001CH Stack pointer H SPH I SP RIW Undefined 003CH Waveform generator scale data registe 0 001DH Stack pointer L SPLI RIW Undefined 003DH Waveform generator scale data registe 1 001EH Processor status 0 PSO RIW Undefined 003EH Waveform generator scale control registe

~I-L £rocessor status 1 PS1 RIW *******0 003FH D/A Control registe NOTES:

• R!W indicates that there is at least one bit in the register is capable of read/write.

(The register indicated by RIW includes the bit of special-purpose register for read). R indicates that the register is only for read.

• * indicates that the corresponding bit is ubdefined.

RIW Iinitial value PO R Undefined

t?

-n

Address Register name RIW Initial Address Register name

0040H TimerO counter H TMOH TMO R OOH 0060H Waveform memory 0 StepOOl01 0041H TimerO counter L TMOL

R

^OOH ^0061H Waveform memory 0 Step02/03 0042H TimerO modular register H TMOMH TMOM R!W FFH 0062H Waveform memory 0 Step04/05 0043H TimerO modular register L TMOML RIW FFH 0063H Waveform memory 0 Step06/07 0044H TimerO capture register H TMOPH TMOP R OOH 0064H Waveform memory 0 Step08/09 0045H TimerO capture register L TMOPL R OOH 0065H Waveform memory 0 Step 10/11 0046H TimerO control register 0 TMOCO R!W COH 0066H Waveform memory 0 Step12/13 0047H TimerO control register 1 TMOC1 RIW 1FH 0067H Waveform memory 0 Step14/15 0048H Timer counter TM1 R OOH 0068H Waveform memO!I 0 Step16/17 0049H Timer1 modular register TM1M RIW FFH 0069H Waveform memO!I 0 Step 18/19 004AH Timer1 control register TM1C R!W 07H 006AH Waveform memory 0 Step20/21 0048H Timer2 counter TM2 R OOH 006BH Waveform memory 0 Step22/23 004CH Timer2 modular reqister TM2M RIW FFH 006CH Waveform memory 0 Step24/25 0040H Timer2 control reqister TM2C RIW 07H 0060H Waveform memory 0 Step26/27 004EH Timer1/2 clock select register TM12CT RIW OOH 006EH Waveform memory 0 Step28/29 004FH Reverse (access disable) 006FH Waveform memory 0 Step30/31 0050H Timer4 counter TM4 R OOH 0070H Waveform memory 1 StepOOl01 0051H Timer3 counter TM3 R OOH 0071H Waveform memory 1 Step02/03 0052H Timer3 control register TM3C R!W OOH 0072H Waveform memory 1 Step04/05 0053H Reverse (Only use for flash memory version) *1 0073H Waveform memory 1 Step06/07 0054H Timer4 modular reqister TM4M RIW FFH 0074H Waveform memory 1 Step08/09 0055H Timer3 modular reqiste TM3M RIW FFH 0075H Waveform memory 1 Ste010/11 0056H Timer4 control reqister TM4C RIW OOH 0076H Waveform memory 1 Step12/13 0057H Memorv confiouration reoister *2 MCF 0077H Waveform memory 1 Step14/15 0058H Timer5 counter TM5 R OOH 0078H Waveform memory 1 Ste016/17 0059H Timer5 modular reoister TM5M R!W FFH 0079H Waveform memory 1 Ste018/19 005AH Timer5 control reqister TM5C RIW 10H 007AH Waveform memory 1 Ste020/21 0058H Reverse (Only use for flash memory version) *1 0078H Waveform memory 1 Ste022/23 005CH Timer6 counter TM6 R OOH 007CH Waveform memory 1 Ste024/25 0050H Timer6 control reqister TM6C RIW 38H 0070H Waveform memory 1 Ste026/27 005EH Watchdoq timer reaister WOT R OOH 007EH Waveform memory 1 Ste028/29

~05FH Watchdoo timer control reoister WOTC RIW 38H 007FH Waveform memory 1 Ste030/31

*1 : These two address are only valid with flash memory version [LU8500FO/F1] and do not exist in SM8500 series.

RIW

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