THE 3851 PROGRAM STORAGE UNIT (PSU)
3.2 SIGNAL DESCRIPTIONS, ELECTRICAL CHARACTERISTICS AND MASK OPTIONS
Figure 3-2 illustrates the 3851 PSU device pins.
Signal names agree with Figure 3-1 and are DBO-DB7 Data Bus Bi-directional (3-State) ROMCO·ROMC4 Control Lines Input
<I>,WRITE Clock Lines Input EXTINT External Interrupt Input PRIIN Priority In Input PRIOUT Priority Out Output INT REO Interrupt Request Output
- -
DBDR Data Bus Drive Output VSS, VDD, VGG Power Supply Lines Input3.2.1 Signal Descriptions
Individual signals are described next. Signal charac-teristics are given in Table 3-2.
<I> and WRITE are the clock outputs from the 3850 CPU.
ROMCO through ROMC4 are the control signals output by the 3850 CPU.
DBO through DB7 are the bi-directional data bus lines which link the 3851 PSU with all other devices in the F8 system.
EXT I NT. A high to low transition on this signal is interpreted as an interrupt request from an external device.
PRI IN. Unless this input signal is low, the 3851 PSU wtll not set INT REO low in response to an interrupt.
PRI OUT. This signal becomes PRI IN to the next device in the interrupt priority daisy chain. PRI OUT is output high unless PRI IN is entering the 3851 PSU low, and the 3851 PSU is not requesting an interrupt.
INT REO. This signal becomes the INT REO input to the 3850 CPU. INT REO must be output low in order to interrupt the 3850 CPU; this only occurs if PRI IN is low, and 3851 PSU interrupt control logic is requesting an interrupt.
I/o
AO throughI/o
B7 are I nput/Output ports through which the 3851 PSU communicates with logic external to the microprocessor system.DBDR is low when the 3851 PSU is outputting data on the data bus (DBO-DB7). For information on using DBDR see Section 3.4.1. DBDR is an open drain signal.
3-5 RBSO 5-'-76
Table 3"2. A Summary of 3851 PSU Signal Characteristics SIGNAL
DATA BUS (DBO-DB7)
CLOCK LINES (<1>, WRITE)
PRIORITY IN AND CONTROL LINES (PRI IN, ROMCO-ROMC4)
PRIORITY OUT (PRI OUT) Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input High Voltage Input Low Voltage Leakage Current Input High Voltage Input Low Voltage Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Leakage Current Output High Voltage Output Low Voltage Leakage Current Input High Voltage Input Low Voltage Input Clamp Voltage Input High Current Input Low Current Input Low Current Output High Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Leakage Current Input Low Current Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage
Table 3-2. A Summary of 3851 PSU Signal Characteristics (Continued)
SIGNAL SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS
I/O PORT OPTION C (DRIVER VOH Output High Voltage 3.75 VDD Volts IOH
=
-1 mAPULL-UP) VOL Output Low Voltage VSS 0.4 Volts IOL
=
2 mANotes:
1. Pull-up resistor to V DD on CPU.
2. Positive current is defined as conventional current flowing into the pin referenced.
3. Hysteresis input circuit provides additional 0.3V noise immunity while internal/external pull-up provides TTL compatibility.
4. Measured while I/O port is outputting a high level.
3.2.2 Mask Options
The following mask options must be specified for every 3851 PSU:
1. The 1024 bytes of ROM storage. This will reflect programs and permanent data table stored in the PSU memory.
2. The 6-bit page select. This defines the PSU address space, as described in Section 3.1.3.
3. The 6-bit I/O port address select. This defines the four PSU I/O port addresses, as described in Section 3.1.10.
4. The 16-bit interrupt address vector, excluding bit 7. This address vector is described in Section 3.6.2, but for a complete understanding of its use, see the Guide to Programming the F8 Microcomputer.
5. The I/O port output option. The choices are between the standard Pull-up (Option A), the Open-Drain (Option B), and the Driver Pull-up (Option C). See Section 3.4.3 for further details.
3.2.3 Card Format Used to Define 3851 PSU Mask Options
Mask options are specified using a card file which may include the following types of card:
• Option card,
• Comment cards,
• 'X' cards (text format commands), and
• 'C' cards (ROM truth table data).
OPTION CARD FORMA T
The option card should always be the first card in the input data file. The format of the option card follows:
is the customer name
is as-digit SL number for the device assigned by FSC
is the ROM number (0-63 decimal) Specifies ROM page
is the decimal number of the first I/O port of the group selected
is 1 for Standard I/O} R f . e er t 0
2 for Open Dram .
3 for Output Only Section 3.4.3 is the Timer/External I nterrupt Address Vector (4 Hexadecimal digits) (Refer to Section 3.6.3)
Columns 58-60 specify the desired number base for the address field on the output listing.
Columns 63-65 specify the desired number base for the data fields on the output listing. Each defaults to DECIMAL when not specified. All other fields on the option card must be specified.
COMMENT CARD FORMA T
Each comment card must have an asterisk (*) in column 1. All other columns are ignored. A comment card may occur any time after the option card in the input file. Comment cards are optional.
TEXT FORMAT CARD FORMAT
The text format commands are used to describe the format of the ROM data cards which follow. Text format commands should have the character 'X' in 3-7
RBSO 5-1-76
column 1 and should precede all ROM data cards.
The valid text format commands are:
X SEQUENCE
indicates that the ROM data has sequence numbers in columns 77-79. This command causes F8 ROM to do sequence checking.
X BASE HEX HEX DEC DEC
specifies the number base of the ROM address input and the ROM data input respectively. If no X BASE
card has occurred
EXAMPLE OF F8ROM INPUT DECK
SUPER ELECTRONICS 3000 0 4 1 0010 Define 3851 PSU Mask Options
Information concerning the use of paper tapes and cartridges as a medium for ordering 3851 PSU custom devices can be obtai ned by contacti ng Fairchild's MicroSystems Division Marketing.
3.2.5 Electrical Specifications
Absolute Maximum Ratings (Above which useful life may be impaired)
VGG VDD
I/O Port Open Drain Option External I nterrupt Input All other inputs & outputs Storage Temperature
SYMBOL PARAMETER MIN. TYP. MAX. UNITS TEST CONDITIONS
For a description of these clock signals, and how they are generated, see Section 2.3.
The WRITE clock refreshes and updates 3851 PSU address registers, which are dynamic.
The <I> clock drives sequencing logic to precharge the ROM matrix. The <I> clock also drives the programmable timer.
3.4 INSTRUCTION EXECUTION
The 3851 PSU responds to signals which are output by the 3850 CPU in the course of implementing instruction cycles. Figure 2-9 illustrates timing for instruction cycles and ROMC signals being output by the CPU.
Table 3-4 summarizes the data bus response of the 3851 PSU to the ROMC states described in Table 2-5.