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3.6 INTERRPUT LOGIC
The 3851 PSU interrupt system is illustrated concep-tually in Figure 3-10. Figures 3-11 and 3-12 show the timer and external interrupt event sequences which occur during interrupt processing.
3.6.1 Interrupt Logic Organization
The Interrupt Control Register (I/O port) has the I/O port address xxxxxx10, where xxxxxx is the 6-bit I/O port address select. Data is loaded into this register (I/O port) using an OUT or OUTS instruction. Data cannot be read out of this register (I/O port). The contents of the Interrupt Control Register (I/O port) is interpreted as follows:
3.3mS
A
A - 200 loaded into timer.
B - First time out.
---.
B
C - Second, and subsequent time outs.
3.953 mS
.,
..-o
D - Interrupt Service Routines being entered by CPU.
CONTENTS OF
I/O PORT INTERPRETATION
B'xxxxxxOO' Disable all interrupts
B'xxxxxx01' Enable external interrupt, disable time interrupt
B'xxxxxx10' Disable all interrupts
B'xxxxxx11' Disable external interrupt, enable timer interrupt
In the above I/O port contents definitions, x represents "don't care" binary digits.
Depending on the contents of the Interrupt Control Register (I/O port), a 3851 PSU's interrupt control logic can be accepting timer interrupts, or external interrupts, or neither, but never both.
3.953 mS
f4-
12---
13.
-C C
o D
11,12,13 - Intervals between time out interrupt request reacing interrupt logic, and service routines being entered by CPU.
Figure 3-9. Time Out and Interrupt Request Timing
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INTERRUPT CONTROL REGISTER IF 1, SET BIT 7 OF
INTERRUPT ADDRESS VECTOR ~
L
TO O. IF 0, SET IT TO 1. ~-r---r----'
H'IJ'
TIME OUT
- - - t D
a
SYNC FF
EDGE DETECT
POSITIVE K J
TIMER INT
FF
a
POSITIVE EDGE
DETECT
a
DSYNC FF
EXTINT
o DURING EVENT G
.---+-.... __ F_R_O_Z_E_N _ _ _ OF FIGURES 3-11, 3-12 (INTERRUPT SERVICE)
1 OTHERWISE
NOTE: ALL FF'S ARE CLOCKED BY WRITE CLOCK. SEE TEXT FOR CLEAR INPUTS TO THE JK FLlp·FLOPS
*"OPEN COLLECTOR" GATE
K J SER REO
a
FFINT REO
PRIOUT
NOTE: ALL FF'S ARE CLOCKED BY WRITE CLOCK. SEE TEXT FOR CLEAR INPUTS TO TH E JK FLIP-FLOPS Figure 3-10. Conceptual Illustration of 3851 PSU Interrupt Logic
EVENTS A B C G H
~ ~ ~
F+ +
WRITE CLOCK (Ll
n
(L)n
(Lln
(5)n
TIME-OUT ~y~
SYNC F.F.
~( J TIMER INT F.F.
INT REO (TO CPU)
~}
ROMC STATE (FROM CPU) 10 1C OF 13 00
(LIS) -... LONG OR SHORT CYCLE
(Ll -... LONG CYCLE (5) -... SHORT CYCLE
Figure 3-11. Timer Interrupt Sequence
EVENTS A B C 0 G H
~ ~ ~
F• •
WRITE CLOCK (Ll
n
(Lln
(Lln
(5)n
EXTINT
~
SYNCH F.F.
n
EXT INT F.F.
INT REO (TO CPU)
L,{
ROMC STATE (FROM CPU) 10
I
1C OF 13 00(LIS) - - . LONG OR SHORT CYCLE (L) - - . LONG CYCLE
(5) - - . SHORT CYCLE
Figure 3-12. External Interrupt Sequence
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Figure 3-10 is a conceptual logic diagram of the PSU's interrupt logic. Between the EXT I NT input or the time-out input and the output I NT R EQ, there are 3 flip-flops. EXT INT and the time-out interrupt input each have a synchronizing flip-flop and edge detect logic.
Each edge detect block is followed by its own INTERRUPT flip-flop which latches the true condition.
The outputs of the TIMER INTERRUPT flip-flop and the EXTERNAL INTERRUPT flip-flop are ORed to set the SERVICE REQUEST flip-flop, providing that an interrupt from some other PSU is not being acknowledged.
INT REQ is the NAND of PRI IN and SERVICE REQUEST.
INT REQ is an open drain signal. The INT REQ signal of several PSUs may be tied together so that anyone can force the line to OV if it is requesting interrupt service; a pull-up to VDD is provided by the 3850 CPU to INT REQ input pin. are always at opposite levels. PR lOUT becomes PR I I N for the next device in the interrupt priority daisy chain, if there is one. The function of the priority daisy chain is to insure that just one device at a time be requesting interrupt service.
The SERVICE REQUEST flip-flop cannot become set if another interrupt request is in the process of being acknowledged anywhere in the system.
Rather, if an interrupt request has been latched into the TIMER INTERRUPT flip-flop, or the EXTER-NAL INTER RUPT flip-flop, the PSU logic waits until after the process of acknowledging the other interrupt has been completed, before setting SERVICE REQUEST. This precaution is necessary to insure that the priority chain is not altered during acknowledgement; chaos would result if half of the interrupt vector came from one device and the second half from some other device.
The SERVICE REQUEST flip-flop is cleared after an interrupt from the PSU has been acknowledged.
3-20
It is also cleared whenever the PSU 's interrupt control register is accessed by an output instruction.
The conditions for setting the TIMER INTERRUPT flop and the EXTERNAL INTERRUPT flip-flop differ slightly. External interrupts must be enabled before the EXTERNAL INTERRUPT flip-flop can be set by a negative going transition of EXT INT. However, TIMER INTERRUPT will be set by a timer TIME OUT, independent of the timer interrupt enable bit. This means that the PSU can detect a time out interrupt that is
requested while the PSU was checking for external interrupts.
The TIMER IN TERRUPT flip-flop is cleared whenever the PSU's timer is loaded, or when its timer interrupt has been acknowledged. The
EXTERNAL INTERRUPT flip-flop is cleared when-ever the PSU 's interrupt control register is accessed by an output instruction, or w hen its external interrupt has been acknowledged.
3.6.2 Interrupt Acknowledge Sequence
Upon receiving an interrupt request, whether from an external source via EXT INT or from the internal timer, the PSU and CPU go through an interrupt sequence which ultimately results in the execution of an interrupt service routine located at the memory address pointed to by the Interrupt Address Vector. Figures 3-11 and 3-12 illustrate the interrupt sequences for the two cases. Events occurring in these sequences are labeled with the letters A through H. Events are described as follows.
EVENTA
-The initial interrupt request arrives. -The falling edge of EXT I NT pin identifies an external interrupt. The rising edge of interval timer output indicates a time-out.
EVENTB-The synchronizing flip-flop in the PSU control logic changes state.
EVENTC-The timer interrupt, or external interrupt flip-flop goes true, indicating the local interrupt logic's ac-knowledgement of the interrupt. The timer interrupt flip-flop will always respond and save the time-out occurrance, whereas the external interrupt flip-flop will only be set at this time if the external interrupt mode is enabled within the local control logic.
EVENTD-The INT REO line is pulled low by the PSU, passing the request for servicing on to the CPU. The
conditions that must be present for this to occur are:
The PRI IN pin must be low.
The proper enable state must exist in the local control logic for the type of interrupt (timer or external).
The system is not already into Event F due to servicing some other interrupt.
EVENTE-The CPU now begins its response to the IN T R E Q line by outputting the unique ROMC state H'10'.
This will only occur when the following conditions are satisfied:
The CPU is executing the last cycle of an instruction (beginning an instruction fetch).
The ICB is enabled (ICB
=
0).The current instruction fetch is not protected (see Table 2-6).
EVENTF-The CPU generates the interrupt acknowledge sequence of ROMC states. See Table 2-6 under INTRPT for details.
EVENTG-At this point the CPU begins fetching the first instruction of the interrupt service routine. I n the
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PSU interrupt logiC, the SERVICE REQUEST flip-flop and the appropriate INTERRUPT REQUEST flip-flop have been cleared.
EVENTH-The CPU begins executing the first instruction of the interrupt service routine.
3.6.3 Interrupt Address Vector
During the interrupt acknowledge, the interrupting PSU provides a 16-bit interrupt address vector. The CPU causes this vector to be loaded into PCO, so that program execution can branch to the routine that handles this particular interrupt. Fifteen bits of the interrupt vector are specified as a mask option. Bit 7 cannot be masked; it is set by the interrupt control logic to 0 if the timer interrupt is enabled or to a 1 if external interrupt is enabled.
So that the interrupt vector looks like:
WWWW, XXXX, OYYY, ZZZZ for timer interrupt
and WWWW, XXXX, 1 YYY,. ZZZZ for external interrupt
where W, X, Y and Z are the mask specified bits.
3.6.4 Interrupt Signals Timing
Timing for signals associated with the 3851 interrupt logic is shown in Figure 3-13.
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,..---,
I \
LONG CYCLE
ROMC STABLE
INTREQ __________
~~---tr--'~~---~I~-.:~~~~~~t_r2 ____ -'~
r=~3~ F~4=i~_
PRIOUT
PRIIN ---~
I
INT REQ
---+-"'"
~ ~1 '= I
PRIOUT
----i
~EXTINT _______________________________________
~tex~
~~---NOTE: TIMING MEASUREMENTS ARE MADE AT VALID LOGIC LEVEL OF THE SIGNALS REFERENCED UNLESS OTHERWISE NOTED.
SYMBOLS ARE DEFINED IN TABLE 3-3
Figure 3-13. Interrupt Logic Signals' Timing