THE 3852 DYNAMIC MEMORY INTERFACE (DMI)
4.5 INSTRUCTION EXECUTION
Like other memory devices of the F8 family, the 3852 OMI responds to signals which are output by the 3850 CPU in the course of implementing instruction cycles.
Figure 4-9 and Table 4-6 summarize sta,tes for the three data transfer control signals (CPU READ, RAM WRITE, REG DR), the contents of the data bus, and the source of memory addresses, for every ROMC state described in Table 2-5.
67095665
4.5.1 Data Output by RAM
Figures 4-5,4-6 and 4-7 provide worst case timing when RAM, controlled by the 3852 OMI, outputs data onto the data bus. I n these figures it is assumed that CPU SLOT is used to strobe the RAM data into the data bus latches. Refresh timing is not shown here (see Section 4.6).
CPU READ is output high by the 3852 OMI to enable transfer of data from the data bus buffers to the data bus. Recall that dynamic RAM have its own connection to the data bus via buffer/latches;
data is not transferred via the 3852 OM I.
Observe that CPU READ high is similar to OBOR low-each is active when its respective data bus drivers are turned on.
4-11 RBSO 5-1-76
Table 4-4. How the Memory Access Periods of an Instruction Cycle are Used OPERATION PERFORMED DURING
FIRST ACCESS SECOND ACCESS THIRD ACCESS
INSTRUCTION CYCLE
No memory access, or read from [PCO] ~ AO - A 15 Latch data on F8 data None memory addressed by PCO. (See Figure bus. Second memory
4-5.) access for DMA or
refresh.
No memory access, or read from [PCO] ~ AO - A 15 Latch data on F8 data Third memory access memory addressed by PCO. (See Figure bus. Second memory not used.
4-6.) access for DMA or
refresh.
Read data from memory addressed by [PCO] ~ AO - A 15 [Other register] ~ AO Latch data on F8
register other than PCO, or read data - 15 data bus. Third
from address register. (See Figure 4-7.) memory access for
DMA or refresh Write data to memory. (See Figure [PCO] ~ AO- A 15 [DCO] ~AO-A15 Access memory to
4-8.) write data. No DMA
or refresh.
[ ] means "contents of register identified within square brackets.
4.5.2 Data Output by the 3852 DMI
As described in Section 4.3, REGDR defines the address space of the address registers within the 3852 DMI.
If a ROMC state received by the 3852 DMI requires data to be output from an address register, then the 3852 DM I will become the selected data source if REGDR is allowed to go high.
Timing is identical to that for the 3851 PSU when outputting onto the data bus as indicated in Figure 3-3, td 7.
4.5.3 Data Input to RAM
Figure 4-7 provides worst case timing when data is written into RAM. Figure 2-11, tdbl provides timing for data output from the accumulator of the 3850 CPU. Data is transferred through tri-state buffers on the data bus and into RAM. (See Section 8 for system configuration examples.)
RAM WRITE is pulsed low by the 3852 DMI to enable the transfer of data off the data bus, into RAM. The tri-state buffers or multiplexers between 4-12
data bus and RAM WRITE data lines are necessary if DMA sources are also allowed to write into RAM.
See Section 4.3 for a discussion of RAM address space.
4.5.4 Data Input to the 3852 DMI
As described in Section 3.1.4, problems of address-ing contention are posed by havaddress-ing duplicated address registers; one step in resolving this possible problem is to force every memory device to read data into its address registers whenever a ROMC state specifies any such operation. Address space concepts therefore do not apply when data is read into 3852 DMI address registers.
4.5.5 Input/Output
There are two versions of the 3852 DM I; each has four reserved I/O port addresses, implemented as follows:
PORT ADDRESSES
FUNCTION
STANDARD OPTION
OC EC General purpose latch
OD ED Memory/DMA control
OE EE Not implemented
OF EF Not implemented
WRITE~ \~I~:~~~~~~~~~~~~~~~~~~~~~~3_.0_M_S::::::::::::::~I-;---·~~
r-
450 nS-1foo1 ..
f----1.25 MS----....,~~, I
ADDRESS LINES I X , - - - S ...
T-A--B-LE---...;I--1
~900 ns----1 ,
I X,--D-A-T-A-ST-A-B-L-E-F ... R-O ...
M-.:...R-A-M-DATA BUS
,.. 2.15 MS
~ I I
- - - - 1 . 2 5 MS---+-l~1
I \
I~---~---I--~~5~1:_ns_1_ ~~~O~
~US~ I~/~---~)I~---rl
...
1 .. ! - - - 2 . 2 7
MS---~-·
200j.--MEMIDLE
--{rl:
nS 750nS--\
I \ I.,..--~\""___
_ ____JI
---1~~0
I.. 1.0MS~I
\ ____ 1
Figure 4-7.3852 DMI Timing Signals Output during a Long Cycle Memory Read, with Address Out of Data Counter
Option port addresses are used in F8 systems that include both a 3852 OMI and a 3853 SMI; it is differentiated from the Standard by a SL30116
marking. .
The implemented I/O ports are accessed via IN, INS, OUT and OUTS instructions, just like any other I/O port. However, the 3852 OMI I/O ports are internal latches, having no connection to I/O pins or external interface. REG DR, if not clamped low by an external device, will go high during I N or I NS instructions that select either of the OM I ports.
However, clamping REGOR low does not inhibit data bus driving during I/O as it did during the output of address registers.
I/O port OC (or EC) is used as a general purpose, 8-bit data storage location.
I/O port 00 (or ED) controls memory refresh and OMA as follows:
67095665
NOT USED
+-BIT NUMBER
1 = DMA disabled.
o = DMA enabled.
1 = Refresh memory.
o = No memory refresh.
L...--_ _ 1 = Refresh every fourth instruction cycle.
o = Refresh every eighth instruction cycle.
4.5.6 System Initialization
An F8 system is initialized by power on, or EXT RESET being pulsed low at the CPU.
When an F8 system is initialized, OMA is turned off and memory refresh is on, with refresh every fourth cycle selected.
Contents of all other registers are indeterminate;
reading the control port 00 (or ED) also gives indeterminate results, although the OMA/refresh state of the OMI has been initialized.
4-13 RBSO 5-1-76
WRITE
-.A . \J:I·========~~~~~~~_-_3_.0_I.I_S~============~-/~==--=-~~l
~450
oS1'"" .. f--- 1 .25. s _ _ _ ---' .. ~I
ADDRESS LINES
---~---~)(r---~~S=TA~BL~E~---~1.3I.1S .. I
I )('---~D~A~T~A~ST~A~B~L~E~F~R~O~M~C~PU~---DATA BUS
MIN M I N r
-r.---1.85I.1S---; .. ~1350 nS I.. ..1 2nOsO
1-RAM WRITE ---t---~
\ ' . ~ '- '/"
CPU READ
CPU SLOT
MEMIDLE
CYCLE REO
14---2.3I.1SMAX---'J-· ~ .. I
----I \~ ________________________________________ __
r450nS~
~:?st~
I \~ ________________________________________ ___
_12nO~I~
~750nS I '.' '- .
- - -
~ '----_~!--I
-'l't-.,}:---,..:::r==--"'~'--J ,50 t I~O:- . } ) , ~. /
. ~ ~
Figure 4-8. 3852 DM I Timing Signals Output during a Write to Memory
CYCLE REO HIGH-TO-LOW TRANSITION IDENTI FI ES A NEW MEMORY ACCESS PERIOD
IS CPU SLOT HIGH?
CPU IS ACCESSING
~ ~
MEMORY TO READ OR WRITE IS RAM WRITE LOW?
!
IS MEM IDLE HIGH?
NO/ \m
VES/
RAM IS BEING REFRESHED
MEMORY AVAILABLE FOR DMA ACCESS
CPU IS WRITING RAM IS BEING READ
Figure 4-9. Interpretation of Signals Output by the 3852 DMI
Table 4-5. Symbols Used in Table 4-6
SYMBOL MEANING
[ ] Contents of register or memory location identified within brackets.
D MAl REF IPCO I f refresh occurs d u ri ng th is access, AO-A5 = Refresh address AS-A 15 = Previous [PCO]
If no refresh during this access, and DMA operation is disabled, AO-A 15 = [PCO]
If no refresh during this access, and DMA operation is enabled, AO-A 15 is in high impedance state
FL/REF/PCO If no refresh during second access, and DMA operation is enabled, AO-A 15 is in high impedance state, but DMA cannot occur If refresh occurred during the second access, then
AO-A 15 maintained from previous access during this third access If no refresh during this access, and DMA operation is disabled,
AO-A 15 = [PCO]
DMA/REF/DCO As DMA/REF/PCO, but substitute [DCO] for [PCO]
DMA/REF/PCl As DMA/REF/PCO, but substitute [PC1] for [PCO]
[[ ]]
[DCO] U [DCO] L [PCO] U [PCO] L [PCl] U [PC1] L 10
67095665
Contents of memory word addressed by contents of register Source data on left of arrow, destination on right of arrow DCO, upper byte
DCO, lower byte PCO, upper byte PCO, lower byte PC1, upper byte PC1, lower byte
In place of PCO in DMA/REF/PCO, or FL/REF/PCO, means:
If Port OC (or EC) selected, AO-A7 = 1111111 A8-A 15 = Port C contents
If Port OD (or ED) selected, AO-A7 = Port D contents A8-A 15 = 1111111
If neither Port OC (or EC) or OD (or ED) selected, AO-A 15 = [PCO]
\
4-15 RBSO 5-1-76
Table 4-6. 3852 DM I Responses to ROMe States
SIGNAL CONDITON OR INFORMATION CONTAINED
SIGNAL NAME FIRST MEMORY ACCESS SECOND MEMORY ACCESS THIRD MEMORY ACCESS (LONG CYCLE ONLY) ROMC
STATE cI> I I I I I I I
r--WRITE
--- ---
ICYCLE REQ I I I
ADDR [PCO] DMA/REF/PCO
DATA BUS INSTRUCTION CODE
00* CPU SLOT 1 0
MEMIDLE 0 1
CPU READ 0 1
REGDR 0 0
ADDR [PCO] DMA/REF/PCO FL/REF/PCO
DATA BUS OFFSET FOR BRANCH
01 CPU SLOT 1 0 0
MEM IDLE 0 1 0
CPU READ 0 1 1
REGDR 0 0 0
ADDR [PCO] [DCO] DMA/R E F /DCO
DATA BUS INSTRUCTIO"N OPERAND
02 CPU SLOT 1 1 0
MEM IDLE 0 1 0
CPU READ 0 1 1
REGDR 0 0 0
ADDR [PCO] DMA/R E F /PCO FL/REF/PCO
DATA BUS INSTRUCTION OPERAND
03** CPU SLOT 1 0 0
MEM IDLE 0 0 1
CPU READ 0 1 1
REGDR 0 0 0
04 SEE OD
ADDR [PCO] [DCO] [DCO]
DATA BUS BYTE FROM CPU, TO BE
STORED IN RAM
05 CPU SLOT 1 1 1
MEM IDLE 0 0 0
CPU READ 0 0 0
REGDR 0 0 0
*This is a long cycle for the DS (op code 30) instruction only.
**This instruction is short for BT (op code 8X). BF (op code 9X). and BR7 (op code 8F) if branch not taken, and for DCI (op code 2A) always.
ROMC
Table 4-6.3852 DMI Responses to ROMC States (Continued)
SIGNAL NAME
SIGNAL CONDITION OR INFORMATION CONTAINED FI RST MEMORY ACCESS
r
SECOND MEMORY ACCESS THIRD MEMORY ACCESS (LONG CYCLE ONLY)
[[PCOll~[PCOl. LOWER BYTE 0
[[PCOll~[DCOl. LOWER BYTE 0
Table 4-6. 3852DMI Responses to ROMC States (Continued)
SIGNAL CONDITION OR INFORMATION CONTAINED
FI RST MEMORY ACCESS SECOND MEMORY ACCESS THIRD MEMORY ACCESS (LONG CYCLE ONL YI
.----
Lr-====-I I
[PCO) DMA/REF/PCO FL/REF/PCO
INTERRUPT VECTOR (OF LOWER BYTE, 13 UPPER BYTE)*
[PCO) DMA/REF/PCO FL/REF/PCO
[[PCO))~[DCO), UPPER BYTE
1 0 0
0 1 0
0 1 1
0 0 0
[PCO) DMA/REF/PCO FL/REF/PCO
BYTE F ROM CPU TO
[PCO) DMA/REF/PCO FL/REF/PCO
[PCO) u, [PC1) u, [DCO) u, [PCO) L, [PC1) L, [DCO) L, BYTE FOR I/O PORT
,
0 00 1 0
0 0 0
0 0 0
[PCO) DMA/REF/IO FL/REF/IO
[SELECTED 10 PORT DATA)
1 0 0
0 1 0
0 0 0
0 1 (IF SELECTED) 1 (IF SELECTED)
Table 4-6. 3852 OMI Responses to ROMC States (Continued)
SIGNAL CONDITION OR INFORMATION CONTAINED SIGNAL NAME
FIRST MEMORY ACCESS SECOND MEMORY ACCESS THIRD MEMORY ACCESS
ROMC (LONG CYCLE ONLY)
STATE
<I> f---I L
r
-WRITE
r=====-
ICYCLE REO I ~
ADDR [Pca] DMA/REF/pca FL!REF/pca
DATA BUS *
1C CPU SLOT 1 a a
MEMIDLE 0 1 a
CPU READ a a a
REGDR a a a
10 SEE aD
ADDR [Pca] [Pca] DMA/REF/pca
1E DATA BUS [Pca]L (1E), [PCa]u{1F)
1F CPU SLOT 1 1 a
MEMIDLE 0 a 1
CPU READ 0 0 0
REGDR 0 1 1
*During INS or OUTS instruction for Port a or 1: I/O data byte. During INS, OUTS, instructions, other ports:
I/O port address. Otherwise not used, and short cycle.
Note:
See Table 4-5 for a description of symbols used in this table.
4.6 MEMORY REFRESH AND DIRECT