---.... ~I
tdbSI "'" .. f-1. Timing for CPU outputting data onto the data bus.
Delay tdb1 is the delay when data is coming from the accumulator.
Delay tdb2 is the delay when data is coming from the scratch pad (or from a memory device).
Delay tdbO is the delay for the CPU to stop driving the data bus.
2. There are four possible cases when inputting data to the CPU, via the data bus lines: they depend on the data path and the destination in the CPU, as follows:
tdb3; Destination - I R (instruction Fetch) - See Figure 2·10 for details.
tdb4; Destination - Accumulator (with ALU operation - AM) tdb5; Destin~tion - Scratch pad (LR K,P etc.)
tdb6; Destination - Accumulator (no ALU operation - LM)
In each case a stable data hold time of 50 nS from the WRITE refrence point is required.
Symbols are defined in Table 2-4
Figure 2-11. Memory Reference Timing
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2-21 RBSO 5-1-76
- - - ,
VDD
OUTPUT STROBE
LATCH
HYSTERESIS CIRCU IT P
VSS
IVDD----I
I I
I II
I L _____ _
TTL DEVICE INPUT
10---L -_ _ _ _ _ _ ~
I
(c)I I I
I L _ _ _ _ _ _ _ .
TTL DEVICE OUTPUT (OPEN-COLLECTOR) Figure 2-12. An FB I/O Port Bit
level at the output of the device, depending on its characteristics. I f the level at P is set high, transistor (d) does not conduct current, and a high level is transferred by (d).
When data is input to the I/O pin, high or low levels at 0 drive the hysteresis circuit in the port, and result in logic 1's or O's being transferred to the accumulator.
Since the I/O pin and the TTL device output at 0 are wire-ANDed, it is possible for the state of one to affect the transfer of data out from the I/O pin or in from the TTL device output. For example, if the latch in the I/O port is set so that the pin is clamped low by (b), then the level at 0 cannot pull P high. Conversely, if P is clamped to a low level by (c), setting the latch for a high level has no effect.
It can be seen, then, that all I/O port bits should be set for a high level, before data input, to prevent incoming logic O's from being "masked" by logic 1's present at the port from previous outputs.
In some instances, the ability to mask bits of a port to logic 1 is useful. (Note that logic 1 becomes
a OV electrical level at the I/O pin; likewise logic
o
corresponds to a high electrical leveL)There are two types of programmed I/O operation that the F8 CPU may execute:
1. I/O via the two CPU ports (0 and 1), 2. I/O via ports on the other devices.
I/O operations that use the two CPU I/O ports execute in two instruction cycles. During the first cycle, the fetched instruction is decoded; the data bus is unused. During the first cycle, data is either sent from the accumulator to the I/O latch or enabled from the I/O pin to the accumulator depending on whether the instruction is an output or an input. At the falling edge of WRITE (marking the end of the first cycle and beginning of the second cycle) the data is strobed into either the latch (OUTS) or the accumulator (INS) respectively.
The second cycle is then used by the CPU for its next instruction fetch. Figure 2-13 indicates I/O timing.
Observe that for the data input (I NS) the set-up and hold times specified are with respect to the
~~~1"'4----PWS--y-_"--_ -_-...J.+i~
(WRITE)../'
1'-"""---1 I
I~---I
I I
~tSU-+/ ~ k-th
DATA MAY CHANGE
X
STABLE :X
DATA MAY CHANGEI/O (1)
I I
I... to -I I
: DATA FROM OLD OUTS XrNEWDATA+: -I/O (2)
(1) This represents the timing for data at the I/O pin during the execution of the I NS instruction, i.e., the CPU is inputting.
(2) This represents the timing for data being output by the CPU at the I/O pin.
Symbols are defined in Table 2-4
Figure 2-13. Timing for Data Input or Output at //0 Port Pins WRITE pulse occurring at the end of the first cycle
in the two cycle instruction. For output data (OUTS) the delay is specified with respect to the falling edge of WRITE marking the beginning of the second cycle in the two cycle instruction.
I/O instructions that address I/O ports with an I/O port address greater than OF 16 occupy two bytes;
the first byte specifies an IN or OUT instruction, while the second byte provides the I/O port address.
Required timing at I/O port pins is given in the section of this manual that describes the device which contains the addressed I/O port.
2.4.7 Interrupts
This section describes timing associated with interrupts, as controlled by the CPU. The general concepts of interrupts has been described in Section 1.4 and use of interrupts, as it relates to other devices and device combinations, are described in other appropriate sections of this manual.
There are three CPU signals with interrupt process-ing; timing for all signals is illustrated in Figure 2-14.
An interrupt sequence is initiated by pulling either INT REO or EXT RES low. In the case of INT REO.
nothing will happen unless ICB is low. Also, nothing will happen until the next interruptable instruction comes to the end of execution. I n the
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case of EXT RES, execution of the interrupt routine will begin in the machine cycle immediately following that in which the signal goes low,
providing the set-up time specified in Figure 2-14 has been met. EXT RES response logic ignores ICB.
In response to INT REO low, when the CPU acknowledges the interrupt, it forces ICB high, and initiates instruction cycles with ROMC states lC, OF, 13 and ~O, in that order. Th is causes program execution to branch to the interrupting device's address vector.
In response to EXT RES low, when the CPU acknowledges the interrupt, it forces ICB high, then initiates instruction cycles with ROMC states lC, 08 and ~O, in that order. This causes program execution to branch to memory location O.
The ICB signal is pulled low by the EI instruction, and is returned high by the 01 instruction.
2.5 INSTRUCTION SET SUMMARY
The 3850 CPU instruction set is summarized in Table 2-7; this table and the accompanying text below does not attempt to teach a reader how to program the F8 microcomputer system, rather this section explains signals and timing associated with the execution of every instruction. The reader who wishes to learn how to write F8 programs should
2-23 RBSO 5-1-76
-.A ~.
PWs / ~ / - - L
WRITE
f.-
PW2~ I
.. PW lI ~I
I
ROMC
~
td3-1 X
TRUE: I
I I
~td4~
I
ICB (1)
><
l:::tds~ I
INT REO (2)
I '\ I
I ..
td s~I I
I I I
INT REO (2)
I
I { ~I
EXT RES
I
tsx(1) ICB will go from a 1 to a 0 following the execution of the EI instruction and will go from a 0 to 1 following either the execution of the DI instruction or the CPU's acknowledgement of an interrupt.
(2) This is an input to the CPU chip and is generated by a PSU or 3853 MI chip. The open drain outputs of these chips are all wire "ANDed" together on this line with the pull-up being located on the CPU chip. For a 0 to 1 transition the delay is measured to 2.0V.
Symbols are defined in Table 2-4 Figure 2-14. Interrupt Signals Timing read "A Guide to Programming the F8
Micro-computer."
Referring to Table 2-7, columns should be inter-preted as described next.
oPCoDE
This is the instruction mnemonic which appears in the mnemonic field of an assembly language instruc-tion, and identifies the instruction.
OPERA ND (S)
If the instruction contains any information in the operand field of the assembly language source code, the information is shown in this column. Arrows identify the portion of object code which represent the operand field. Any portion of object code that
does not represent the operand field must represent the mnemonic field. Table 2-6 explains symbology used in the operand field.
OBJECT CODE
This is the hexadecimal representation of the instruction's object code. The first byte of object code, or in some cases the first hexadecimal digit of object code, represents the Op Code. The operand is represented by the second and third bytes of object code, if present, or in some cases by the second hexadecimal digit of the first object code byte. Table 2-6 explains symbology used in the object code field.
CYCLE
This column identifies each instruction cycle for every instruction. Every cycle is I isted on a separate
horizontal line, and is identified by the letter S for a short (4 clock period) cycle, or the letter L for a long (6 clock period) cycle. Thus the entry:
S
represents an instruction that executes in one short cycle. The entry:
S L S
represents an instruction that executes in three cycles; the first is a short cycle, the second is a long cycle, the third (and last) is a short cycle.
ROMCSTATE
This is the state, as identified in Table 2-5, which is output by the 3850 CPU in the early stages of the instruction cycle.
TIMING
Timing for all instructions, except I NS and OUTS accessing I/O ports 0 and 1, can be created out of Figures 2-10 and 2-11. For the exceptions, Figure 2-13 is required. The ROMC lines are always set after a delay of td3, as shown in Figure 2-10. The only timing variations for each instruction cycle are data bus timing variations. Therefore data bus timing is defined using the delays tdb1 through tdb6' With the exception of tdb3, these time delays are unambiguous, in that they are keyed to either the leading edge, or to the trailing edge of WRITE high, for either a long instruction cycle, or for a short instruction cycle, as illustrated in Figure 2-11.
There are two cases for tdb3, however, as illustrated in Figures 2-10A and 2-10B; these are identified in Table 2-7 as 3S for Figure 2-10A, and 3L for Figure 2-1 OB. tdb1 through tdb6 are otherwise identified by the numbers 1.through 6.
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Cycles that do not use the data bus are identified by 0 in the timing column; Figure 2-9 illustrates timing in this case. In summary:
o
represents Figure 2-91 represents tdb1 in Figure 2-11 2 represents tdb2 in Figure 2-11 3S represents tdb3 in Figure 2-10A 3L represents tdb3 in Figure 2-108 4 represents tdb4 in Figure 2-11 5 represents tdb5 in Figure 2-11 6 represents tdb6 in Figure 2-11 STATUS FLAGS
Status flags are identified as follows:
o -
OverflowZ - Zero C - Carry S - Sign
Within each column, symbology is used as follows:
Status not effected
o
Status set to 01/0 Status set to either 1 or 0, depending on the results of the instruction's execution
INTERRUPT
An x in this column identifies an instruction that disallows interrupts at the end of the instruction's execution. A y identifies cycles in which the ICB bit is reset to 0 (cleared).
FUNCTION
The effect of each instruction cycle is described in this column using symbology given in Table 2-6.
Observe that instructions are described in Table 2-7 in order to ascending instruction (first byte) object code.
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7 ACCUMULATOR 0 LR r,A
Figure 2-15. Instructions that Move Data between the Scratchpad and Registers