S WHAT IS THE SETUP UTILITY?

Setup is a utility program that allows the operator to parameterize a supervisor diagnostic prior to execution. This is valid for either XXDP+ or ACT/SLIDE environments. Setup asks the hardware and software questions and builds the P-Tables.

The commands available under Setup are:

List - list supervisor diagnostics Setup - create P-Tables

Exit - return control to the supervisor The format for the List command is:

LIST DDN:FILE.EXT

Its function is to type the file name and creation date of the file specified if it is a revision C or later supervisor diagnostic. If no file name is given, all revision C or later supervisor diagnostics will be listed. The default for the device is the system device and wildcards are accepted.

The format for the Setup command is:

SETUP DDN:FILE.EXT= DDN:FILE.EXT

It will read the input file specified and prompt the operator for information to build P-Tables. An output file will be created to run in the environment specified. File names for the output and input files may be the same. The output and input device may be the same. The default for the device is the system device and wildcards are not accepted.

C-5

GLOSSARY

ACKNOWLEDGE (ACK):

Indicates that the previous transmission block was accepted by the receiver and it is ready to accept the next block of the transmission.

ARITHMETIC LOGIC UNIT (ALU):

Allows the microprocessor to perform arithmetic and logic operations.

A PORT:

Read/write input to the multiport RAM.

ASYNCHRONOUS TRANSMISSION:

Transmission in which time intervals between transmitted characters may be of unequal length.

Transmission is controlled by start and stop elements at the beginning and end of each character.

Also called Start-Stop transmission.

BUFFERED ARITHMETIC LOGIC UNIT (DALU):

Operations performed by the ALU are buffered by the BALU and directed to data memory, respective registers, and the Berg Port.

BERG PORT:

An 8-bit port that allows the microprocessor to communicate with other devices without using the UNIBUS.

BIT-STUFF PROTOCOL:

Zero insertion by the transmitter after any succession of five continuous ones designed for bit-oriented protocols such as 18M's Synchronous Data Link Control (SDLC).

BITS PER SECOND:

Bit transfer rate per unit of time.

B PORT:

Read Address input of the multiport RAM (Read Only Port).

BRANCH REGISTER (BRG):

Temporary card storage register used for branch determination and shifting right.

DUFFER:

Storage device used to compensate for a difference in the rate of data flow when transmitting data from one device to another.

CCITT:

Comite Consultatif Internationale de Telegraphie et Telephonie - An international consultative committee that sets international communications usage standards.

CONTROL AND STATUS REGISTERS (CSRs):

Communication of control and status information is accomplished through these registers.

CRC (CYCLIC REDUNDANCY CHECK):

An error scheme in which the check character is generated by taking the remainder after dividing all the serialized bits in a block of data by a predefined number.

CROM:

Plug-in control read only memory used as the instruction memory for the processor.

CYCLIC REDUNDANCY CHECK (CRC):

An error detection scheme in which the check character is generated by taking the remainder after dividing all the serialized bits in a block of data by a predetermined binary number.

DATA LINK ESCAPE (OLE):

A control character used exclusively to provide supplementary line control signals (control char-acter sequences or OLE sequences). These are two-charchar-acter sequences where the first charchar-acter is OLE. The second character varies according to the function desired and the code used.

DATA MULTIPLEXER (DMUX):

An 8-bit wide, 8-to-1 multiplexer used to select data for the B input of the ALU.

DATA-PHONE DIGITAL SERVICE (DDS):

A communications service of the Bell System in which data is transmitted in digital rather than analog form, thus eliminating the need for modems.

DESTINATION ROM (DROM):

Controls the operand as defined by the destination of the instruction in the instruction register.

DIGITAL DATA COMMUNICATIONS PROTOCOL (DDCMP):

DIGITAL's standard communications protocol for character oriented protocol.

DIRECT MEMORY ACCESS (DMA):

Permits I/O transfers directly into or out of memory without passing through the processor's general registers.

ELECTRONIC INDUSTRIES ASSOCIATION (EIA):

A standards organization specializing in the electrical and functional characteristics of interface equipment.

FROM:

Function ROM - Controls up to 16 functions performed by the ALU.

FULL-DUPLEX (FOX):

Simultaneous two-way independent transmission in both directions.

FIELD REPLACEABLE UNIT (FRU):

Refers to a faulty unit not to be repaired in the field. Unit is replaced with a good unit and the faulty unit is returned to a predetermined location for repair.

FIFO:

First In/First Out characteristic of the silo hardware buffer.

HALF-DUPLEX (HDX):

An alternate, one-way-at-a-time independent transmission.

IBUS/OBUS:

Microprocessor NPR control, miscellaneous registers. and CSRs.

IBUS* /OBUS*:

Microprocessor NPR control, miscellaneous registers. and CSRs.

INSTRUCTION REGISTER (IR):

Contains the instruction that is being executed. Outputs are used to control the microprocessor.

LINK MANAGEMENT:

The link management component resolves the transmission and reception on links that are con-nected to two or more transmitters and/or receivers in a given direction.

LU IBUS:

The line unit input data bus provides a path to the DMUX via the berg connector.

MEMORY ADDRESS REGISTER (MAR):

Controls the data memory for buffered arithmetic and logic operations to main memory.

MAIN MEMORY (MEM):

Data storage area for the microprocessor 4K X 8 RAM~ cannot be accessed directly by the CPU.

MAINTENANCE INSTRUCTION REGISTER (MIR):

Provides a destination for an instruction that can be loaded by the CPU during maintenance.

MOP:

Maintenance operation protocol.

MULTIPORT RAM:

Contains all M8207 control and status registers between the microprocessor and the CPU proces-sor.

NEGATIVE ACKNOWLEDGMENT (NAK):

I ndicates that the previous transmission block was in error and that the receiver is ready to accept a retransmission of the erroneous block (also a Not Ready Reply to a station selection in multi-port).

NON-PROCESSOR REQUEST (NPR):

Direct memory access type transfers, see DMA.

PROGRAM COUNTER (PC):

A 14-bit counter used to control the address of the control ROM directly. PC is derived from Branch and Move instructions.

PROTOCOL:

A formal set of conventions governing the format and relative timing of message exchange be-tween two communicating processes.

RANDOM ACCESS MEMORY (RAM)