RESET OPERATION

The following paragraphs describe the operation of the MC68851 in response to an external reset.

The timing for the reset operation is detailed in SECTION 12 ELECTRICAL SPECIFICATIONS.

4.1.1 Initialization of Internal State

The assertion of the RESET input by an external device initializes the MC68851 to a known, idle state by clearing the enable (E) bits in the translation control register (TC) and in each of the eight breakpoint control registers (BACO-BAC7), and clearing the ALC field of the AC register.

Clearing of the E bit of the translation control register disables the address translation mechanism of the MC68851 and causes logical addresses LA8 through LA31 to be passed directly through (unmapped) to the physical bus. The physical address strobe is asserted for all non-CPU space translations regardless of the state of the E bit; however, no access right checking is performed when the translation mechanism is disabled.

Clearing the E bit of the breakpoint control registers disables all breakpoint operations. If a break-point acknowledge cycle is executed by the CPU while the breakbreak-point acknowledge functions are disabled, the MC68851 responds by asserting bus error (BERR). Clearing the ALC field of the AC register inhibits RAL, WAL, and CAL access level checking.

4.1.2 Bus Interface Initialization

Several characteristics of the bus operations of the MC68851 are system-configurable. The infor-mation that determines this configuration is latched from the data bus at the end of the reset sequence (i.e., at the rising edge of the RESET input).

While the RESET input is asserted, the MC68851 asserts the DBDIS output, allowing its data bus to be isolated from all other bus drivers. The condition of both RESET and DBDIS being asserted can be used to gate configuration information onto the MC68851 data bus.

The use of the data bus for MC68851 configuration, as discussed in the following paragraphs, is valid only during reset operation and only the least significant byte of the bus is used. The three higher-order bytes of the data bus are ignored during reset.

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4.1.2.1 DO. This input must be either pulled high (logic one) or left floating during the reset sequence.

4.1.2.2 BUS SIZE (01, 02). D1 and D2 specify the minimum data bus size that connects the MC68851 to any device that may access its internal registers using the coprocessor interface. If multiple logical devices are capable of accessing the MC68851 registers, the maximum size for a single transfer is limited to the size of the smallest of the data buses.

When accessed as a slave device, the MC68851 responds with a DSACKx encoding that indicates the port size as specified on D1 and D2 during reset.

Table 4-1 shows the D1, D2 encodings for various bus width configurations. The default value (D2, D1 left in high-impedance state) is 32 bits.

4.1.2.3 DECISION TIMEOUT DELAY (03, 04). D3 and D4 specify an additional, if any, amount of delay for the MC68851 internal decision-timeout circuitry used to determine when the compare logic of the address translation cache has generated a correct decision. This additional delay is defined from the clock edge on which the bus control signals (PAS, BERR, HALT, and LBRO) would normally be asserted by the MC68851 in the absence of a timeout delay and results in a delay of the assertion of these signals by an integral number of half-clocks as specified by the encoding of D3, D4. These encodings are shown in Table 4-2.

The additional timeout delay is provided for proper operation of MC68851 devices that have a mismatch between the clock speed and the speed of the address translation cache. If the address translation cache decision logic requires more time to validate an access than is available, as determined by the operating frequency and translation time, it is then necessary to delay the assertion of the bus control signals until that validation can be made. Otherwise, correct func-tionality of the address translation and protection mechanisms cannot be guaranteed since the bus control strobes may be activated before valid decisions have been made.

The default additional timeout delay is zero and this can be obtained by either forcing both D3 and D4 high (logic one) or by leaving both in the high-impedance state during reset.

4.1.2.4 FAST TABLE SEARCH (05). During all table search operations, the MC68851 always (except as described below) asserts the physical bus control strobes with the same timing as that of the MC68020. That is, the strobes are asserted on the first falling edge of the clock after initiation of the bus cycle (the falling edge of S1). Normally, during address translations the control strobes

D2 0 0 1 1

Table 4-1. Coprocessor Data Bus Size Specification

Table 4-2. Additional Decision Timeout Delay

are also asserted on a falling clock edge; however, the additional decision timeout delay specified on D3 and D4, as described above, may alter this.

In order to facilitate operation in systems that use the control strobes (for example, PAS) in a synchronous manner (i.e., the signal relationship to a clock edge is important), the MC68851 can be configured such that the control signals are always asserted on the same clock edge regardless of whether a translation or a table search is taking place. In this type of synchronous system, if the decision timeout delay is set such that the bus control signals are asserted on the rising edge of the clock during address translations, it may be desirable to also have them asserted on the rising clock edge during table search operations.

If D5 is held low (logic zero) during reset, the MC68851 asserts the bus control strobes on the same edge of the system clock during both address translation and table search operations. The edge on which the signals are ass~rted is determined by the decision time-out delay indicated on D3 and D4. If D5 is driven high (logic one) or left in the high-impedance state during reset, the MC68851 will not delay the assertion of the bus control strobes when performing table search operations and will always assert PAS on the first falling edge of the clock for these bus cycles (bus state S1).

4.1.2.5 EARLY PROCESSING STARTUP (06). D6 specifies whether the exception processing hardware of the MC68851 is enabled as soon as an exception (any operation by a logical bus master that requires a table search by the MC68851) is detected or delayed until the MC68851 has received control of the logical bus and has asserted logical bus grant acknowledge (LBGACK).

There are two factors to be considered when selecting this mode. If the early processing startup is selected, the exception processing hardware is activated as soon as the exception is detected and six clock periods of the startup overhead are overlapped with the termination of the current logical bus cycle and arbitration for the logical bus. However, the early startup poses a potential problem since the MC68851 initiates processing prior to becoming logical bus master.

In order to correctly service an alternate logical bus master, the MC68851 must be ready to perform address translations as soon as that master gains control of the logical bus. In order to perform this service, the exception processing hardware of the MC68851 must be completely idle and ready for the next translation and, for certain exception conditions, eight clock periods are required to bring the exception processing hardware into the idle state. The MC68851 prevents conflicts between logical bus traffic and the exception processing hardware by delaying the assertion of the logical bus grant output (LBGO) in response to a logical bus request (LBRI), if necessary, by the eight clock periods (maximum) required to idle the exception hardware. If the early startup mode is not enabled, then this delay is not imposed and the worst case arbitration latency for the logical bus is reduced by seven clock periods.

If the early processing startup is enabled, by leaving D6 in the high-impedance state or driving it high (logic one), the normal overhead required for the MC68851 to acquire the logical bus and initiate service for the CPU (for example, table search, ... , etc.) is reduced by six clock periods.

If D6 is pulled low (logic zero), the MC68851 does not initialize its exception processing hardware until it asserts LBGACK. In this case, the worst-case LBGI to LBGO delay is reduced by seven clock periods, but the overhead for all MC68851-initiated operations is increased by six clock periods.

The system designer must balance the above two criterion when selecting this mode of operation.

It is possible to completely avoid the LBGI to LBGO delay imposed by the MC68851 through the use of external arbitration circuitry. Since the response of the MC68851 to a given arbitration sequence is defined, external logic may be employed to bypass the MC68851 bus grant circuitry

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such that the bus request-to-bus grant latency is defined by the bus arbitor of the CPU as opposed to the latency of the CPU plus that introduced by the MC68851. Note that this method mandates use of the MC68851 without the early processing startup mode enabled (i.e., D6 must be driven low during reset). This method is not described in detail in this manual; however, the operation of the logical bus arbitration circuitry is explained in detail in 4.4 LOGICAL BUS ARBITRATION.

4.1.2.6 ASSERTION INHIBIT (07). D7 specifies whether or not CLI is to be asserted during all MC68851-initiated bus cycles. It is unlikely that external caching of MC68851 initiated accesses would be of value, but this decision is left to the system designer.

If D7 is pulled high (logic one) or left in the high-impedance state, CLI will be asserted for all . . MC68851-initiated bus cycles. Otherwise, CLI will not be asserted during these bus cycles.