INSTRUCTION DIALOGS

The following paragraphs detail the coprocessor communication dialogs that are executed by the MC68851 and MC68020 during each memory management instruction. In this discussion, a dialog refers to the sequence of command and data transfers to/from the MC68851, and the service request primitives that are returned to control that sequence. Although the following discussion assumes that the main processor is an MC68020, information is also presented that may be used by designers of systems that utilize a different main processor.

The diagrams presented in the following paragraphs represent the activity of the MC68020 and the MC68851 during the execution of an MC68851 instruction. In these diagrams, boxes are used to depict periods of time during which a device is actively participating in the execution of an instruction; the absence of a box during a period indicates that a device is waiting on the other one to complete an operation.

Each box in the following diagrams is labeled to indicate the activity depicted by that box. The labels above or to the right of the boxes identify the actions taken by the main processor, while the labels below or to the left of the boxes identify the encoding of the response CIR at any time during a dialog. Usually, when a response CIR encoding is indicated, the encoding will be received by the main processor any time that the response CIR is read until the next primitive encoding

MC68851 USER'S MANUAL MOTOROLA

9-15

Primitive

Table 9-7. Me6SSS1 Primitive Responses

Primitive

Type Comments

Null CA = 0, PC = 0, IA = 0, PF = 1, TF = 0

CA = 0, PC = 0, IA = 0, PF = 1, TF = 1

Evaluate and Transfer Effective Address CA = 0, PC = 0

Transfer Single Main Processor Register DO

CA = 0, PC = 0, DR = 0 (Main Processor to MC68851) 01

Evaluate (ea) and Transfer Data Quad Word (Memory Only)

CA = 0, PC = 0, DR = 0 (External to MC68851) Byte Word Long Word

Take Pre-Instruction Exception F-Line Emulation

PC = 0 Protocol Violation

Take Post-Instruction Exception Configuration Error

PC = 0 Illegal Operation

Access Violation

Transfer Single Main Processor Register AO

CA = 0, PC = 0, DR = 1 (MC68851 to Main Processor) A1

Evaluate (ea) and Transfer Data Quad Word (Memory Only)

CA = 0, PC = 0, DR = 1 (MC68851 to External) Byte

Transfer Single Main Processor Register DO

CA = 1, PC = 0, DR = 0 (Main Processor to MC68851) 01

Evaluate (ea) and Transfer Data Quad Word (Memory Only)

CA = 1, PC = 0, DR = 0 (External to MC68851) Byte Word Long Word

Me688S1 USER'S MANUAL

is indicated. Additionally, if the MC68020 fails a supervisor check performed as the result of the MC68851 supervisor check primitive, the resulting trap is the privilege violation exception.

In all of the following paragraphs, the following assumptions are made:

1) Before the start of an instruction dialog, except for the PSAVE and PRESTORE instructions, the MC68851 is in the idle state,

2) The MC68020 and the MC68851 communicate via a 32-bit data bus, and 3) The memory width is 32 bits, and all memory operands are long-word aligned.

9.3.1 General Instructions

This group of instructions includes the MC68851 instructions: PFLUSH, PFLUSHA, PFLUSHR, PFLUSHS, PLOADR, PLOADW, PMOVE, PTESTR, PTESTW, and PVALID. The common factor be-tween these instructions is the format of the F-line operation word, which uses the CpGEN format of the M68000 Family coprocessor instruction set (refer to the MC68020 32-Bit Microprocessor User's Manual. Thus, the initial phase of the communication dialog for these instructions is identical, with the MC68020 writing the command word to the MC68851 and then relying on the MC68851 to control the remainder of the dialog through the use of the coprocessor interface response primitive set.

In general, the dialog for an MC68851 instruction does not advance to the next state until all activity has been completed in the current state. The MC68851 enforces this by controlling the assertion of the data transfer and size acknowledge (DSACKx) signals and through the use of the come-again attribute of the response primitives.

The following paragraphs discuss the different protocols that are used by the MC68851 for this group of instructions.

9.3.1.1 PFLUSH INSTRUCTIONS. The dialogs for these instructions are initiated by a write to the command register and a read of the response register.

The PFLUSH instruction may require that one of the main processor function code registers (SFC of DFC) be transferred if a function code is required for the flush operation and the value is not encoded in the coprocessor operation word. If the transfer of SFC or DFC is required, the MC68851 issues a transfer main processor control register primitive and indicates the required register in the register select CIR. Alternately, the function code may reside in one of the main processor data registers. If so, the MC68851 will issue the transfer single main processor register primitive to have the appropriate register transferred. After the function code transfer is complete (if re-quired), the evaluate and transfer effective address primitive is issued requesting the calculation and transfer of an effective address from the main processor to the MC68851 for use in the flush operation. The MC68851 performs the flush operation and releases the processor upon comple-tion. Until the flush is complete, the MC68851 does not terminate the write cycle accessing the operand address CIR (Le., the DSACKx signals are not asserted). This ensures that the next cycle is translated correctly.

The supervisor check for these instructions may be returned either before or after the function code transfer (if any) but always occurs before any entries are flushed from the ATC.

The dialogs for the PFLUSH instructions are shown in Figures 9-18 and 9-19. The key for all instruction dialogs presented in this section are shown in Figure 9-19.

9.3.1.2 PLOAD INSTRUCTIONS. The dialog for these instructions is similar to that used during the PFLUSH instructions. The major difference in the communication required for these

instruc-MC68851 USER'S MANUAL MOTOROLA

9-17

co~ .!..o

00-1

o

:xJ

o s;:

:s:

n

en co co U1

...

c en m :::IJ

en :s:

»

2 C

»

r-TRANSFER SINGLE MAIN PROCESSOR REGISTER (CA=!. DR=O. PF=O)

MC6BB51 MC6B020

NULL (CA=O, PF=1)

cB

DECODE INSTRUCTION

$0802

WRITE COMMAND FLUSH BY LOGICAL ADDRESS &

~

FC FLUSH BY FC ONLY

Fe IN DATA

REG~

FC IN COMMAND WORD ^{SFC DR}

TRANSF~

^Ofe

l

r

PROCESSOR CONTROL REGISTER

~

READ RESPONSE

(CA=!. DR=O. PF=O)

rn

^{REGISTER NULL} TRANSFER CONTROl

c:a

ITRAP IF S ' " NOT SET _ P""", .OI"ONI

READ RESPONSE MC68851 SPECIFIES SFC OR DFC READ REGISTER SELECT SUPERVISOR CHECK READ RESPDNSE

TRANSFER DATA ILLEGAL ($0 OR $1) CIR PERFORM SUPERVISOR CHECK

EVALUATE AND'TRANSFER EFFECTIVE ADDRESS (CA=l. DR=O. PF=O)

FLUSH ATC NULL (CA=O. PF=l)

$0802

REGISTER ~

FC IN DATA

REG~ I ^~N

SFC OR DFC

______ FC IN COMMAND WORD TRANSF~

READ RESPONSE

I

PROCESSOR CONTROL REGISTER

rn

READ RESPONSE

TRANSFER SINGLE MAIN (CA=O. DR=O. PF=O)

PERFORM SUPERVISOR

C~ECK

PROCESSOR REGISTER

rn

READ RESPONSE MC68851 SPECIFIES READ REGISTER

(TRAP IF S BIT NOT SET (CA=O. DR=O. PF=O) SFC OR DFC (OR ILLEGAL) SELECT CIR

PRIVILEGE VIOLATION) I

READ RESPONSE EVALUATE <ea>

TRANSFER EFfECTIVE ADDRESS ~

READ RESPONSE Me5885. flUSHES ATe

W

L ^~

NEXT OPERATION

Figure 9-18. PFLUSH and PFLUSHS Instruction Dialog

TRA~SFE~~GlSTEIL... ~ ONLY IF FC IN CPU AND/OR READ RESPONSE REGISTER

MC6BB51 MC6B020

NULL (CA=O, PF=I) ~ OECOOE INSTRUCTION

$0802

WRITE COMMANO SUPERVISOR CHECK REAO RESPONSE

PERFORM SUPERVISOR CHECK

(TRAP IF S BIT NOT SET - PRIVILEGE VIOLATION)

PFlUSHR

~

PFlUSHA

EVALUATE EFFECTIVE AOORESS

~,--

^{- - ,}

ANO TRANSFER DATA READ RESPONSE

I

(CA=O, DR=O, LEN = B) _EVALUATE <ea> flUSH ATC

OJ

READ RESPONSE flUSH ATC AND RPT TRANSFER <ea>

KEY:

NEXT OPERATION INDICATES AN OPERATION THAT IS PERFORMED

ONLY FOR CERTAIN CASES OF THE INSTRUCTION OR OPERATION BEING EXECUTED. THESE OPERATIONS ARE IDENTIFIED EXPLICITlY IN THE DIAGRAMS AS TO THE CONDITIONS UNDER WHICH THEY ARE EXECUTED.

ITALICS INDICATES THE ENCODING OF THE RESPONSE CIR AT POINTS IN AN INSTRUCTION DIALOG WHERE IT WILL NORMALLY NOT BE READ BY THE MC6B020.

THIS INFORMATION IS INCLUDED FOR DESIGNERS OF SYSTEMS THAT DO NOT UTILIZE THE MC6B020 AS THE MAIN PROCESSOR. WHEN AN ENCODING IS INDICATED FOR THE RESPONSE CIA. IT IS NOT CHANGED UNTIL A NEW ENCODING IS GIVEN.

Figure 9-19. PFLUSHA and PFLUSHR Instruction Dialog

tions is that the MC68851 must take control of the logical bus in order to perform a search of the address translation tables (refer to 4.2.3.4 NORMALLY TERMINATED ADDRESS TRANSLATION WITH RELINQUISH REQUEST). The MC68851 requests bus mastership simultaneously with the termination of the effective address transfer accessing the operand address CIR.

During the table search operation it is possible for an alternate higher priority bus master to request and receive control of the logical bus, preempting completion of the MC68851 operation.

The state of the coprocessor instruction is always maintained although the table search may have to be restarted. However, unless a PSAVE is executed priorto access and a PRESTORE is executed prior to returning control to the main processor, alternate bus masters must not be allowed to access the MC68851 coprocessor interface register set during instruction execution as this may cause the context of the instruction in progress to be permanently lost. Systems employing multiple devices capable of accessing the MC68851 registers must provide for synchronization of instruction execution (refer to APPENDIX C SOFTWARE CONSIDERATIONS).

The only difference between the PLOADR and PLOADW instructions is that the translation tables are updated for a read or a write cycle, respectively, during the table search. The dialog for the PLOAD instructions is shown in Figure 9-20.

9.3.1.3 PMOVE INSTRUCTION. The dialogs for this instruction are used for all move operations to and from the MC68851 register set.

Me68851 USER'S MANUAL MOTOROLA

9-19

TRANSFER SINGLE MAIN PROCESSOR REGISTER (CA=1, OR=O, PF=OI

MOTOROLA 9-20

MC68851 MC68020

NULL (CA=O, PF=I)

cB

DECODE INSTRUCTION

$0802

WRITE COMMAND

Fe IN OATA

REGIS~

IN SFe OR OFe

______ FC IN COMMAND WORD TRANSFE~

I

PROCESSOR CDNTROL REGISTER

~

READ RESPONSE (CA=!. DR=O, PF=OI

MC68851 SPECIFIES SFC OR DFC

rn

TRANSfER OATA ILLEGA,

~a"

^$I)

rn

^{REGISTER NULL}

READ RESPONSE READ REGISTER SELECT CIR

TRANSFER CONTROL REGISTER

READ RESPONSE PERFORM SUPERVISOR CHECK

(TRAP IF S BIT NOT SET - PRIVILEGE VIOLATIONI EVALUATE AND TRANSFER EFFECTIVE

ADDRESS (CA=1l. DR=O, PF=OI

MC68851 TERMINATES TRANSFER AND ARBITRATES FOR BUS MASTERSHIP

-6-READ RESPONSE

EVALUATE EFFECTIVE ADDRESS TRANSFER EFFECTIVE ADDRESS

TABLE SEARCH COMPLETED TABLE SEARCH ABORTED BY NORMALLY LOGICAL BUS TRAFFIC

NULL (CA=O, PF=11 WITH

RELINQUISH AND RETRY READ RESPONSE

NULlICA,a, PF'11

~ ^I

READRESpONS!

$0802 I NEXT OPERATION

Figure 9-20. PLOAD Instruction Dialog

TABLE SEARCH ABORTED BY LOGICAL BUS TRAFFIC

MC68851 USER'S MANUAL

Dans le document Address Translation . . (Page 195-200)