The MC68851 is a high-performance paged memory management unit designed to interface to the MC68020 as a coprocessor. This device fully supports the MC68020 virtual machine architecture, and is implemented in HCMOS, a low-power, small geometry process. This process allows both CMOS and HMOS (high density NMOS) gates to be combined on the same device. CMOS structures are used where speed and low power are required, and HMOS structures are used where minimum silicon area is desired. Using this technology enables the MC68851 to be very fast while consuming less power, and having a smaller die size than is feasible with older technologies.
The MC68851 can also be used as a peripheral processor in systems where the MC68020 is not the main processor (e.g., the MC68010 and MC68012). The configuration of the MC68851 as a peripheral processor or coprocessor may be completely transparent to user mode software (i.e., the same user object code may be executed in either configuration with appropriate emulation software for the coprocessor interface).
The architecture of the MC68851 appears to the user as a logical extension of the M68000 Family architecture. Because of the coprocessor interface, the MC68020 programmer can view the MC68851 registers as though the registers were resident in the main processor. Thus, the MC68020/MC68851
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device pair appears to be one processor that has registers for data storage, address pointers, • . general control, translation and protection control, and breakpoint functions.
The MC68851 programming model is shown in Figure 1-1, and consists of the following:
• Three 64-bit root point registers, one each pointing to the root of user, supervisor, and DMA translation tables (CRP, SRP, and DRP).
• A 32-bit translation control register containing configuration information for the MC68851 (TC).
• A 16-bit cache status register that provides information concerning the MC68851 internal translation cache (PCSR).
• A 16-bit status register that contains status and access rights information for a given logical address (PSR).
• Three 8-bit protection control registers used in the privilege checking mechanism (CAL, VAL, and SCC).
• A 16-bit access control register that contains configuration information for the privilege mechanism (access control - AC).
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Figure 1-1. MC68851 Programming Model
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• Eight 16-bit breakpoint acknowledge data registers that ptovide replacement opcodes during MC68020 breakpoint acknowledge cycles (BADO-BAD7).• Eight 16-bit breakpoint acknowledge control registers that contaih enable and count functions for the instruction breakpoint capabilities of the MC68020 and MC68851 (BACD-BAC7).
As shown in Figure 1-2, the MC68851 can be viewed as being composed of eight major elements:
the bus interface (BIU), the address translation cache (ATC), the root pointer table (RPT), the execution unit (EU), the control store, the control logic, the address translation sense circuit, and the register decode logic.
The address translation cache contains 64 recently-used translation descriptors and the control circuitry required to monitor access rights and to create new ATC entries. The ATC itself is composed of three major components: the content-addressable-memory (CAM) containing the logical address and access rights information to be compared against incoming logical addresses, the physical address store that contains the physical address associated with a particular CAM entry, and the control section containing the entry replacement circuitry that implements the replacement algorithm (a variation of the least-recently-used algorithm).
The RPT contains a cache that stores the eight most recently used values of the CPU root pointer and a task alias that is associated with each of the stored values. The root pointer caching and task alias maintenance performed by the RPT allows translation descriptors for multiple tasks to reside in the ATC simultaneously.
The bus interface unit controls the interface to both the logical and physical buses. Included in the BIU are the buffers for both the logiCal and physical address buses and the hardware necessary to perform bus cycles in the physical address space. Also included in the BIU are the bus arbitration state machines for both the logical and physical buses.
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BUS INTERFACE
ADDRESS TRANSLATION UNIT
CACHE
CONTROL
lOGIC CONTROL
EXECUTION STORE
UNIT
REGISTER DECODE
Figure 1-2. MC68851 Simplified Block Diagram
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The register decode section contains the logic required to monitor the logical bus for accesses to its register set internally such that no external decoding of addresses is required.
The address transition sense circuitry continuously monitors the logical address bus to detect any transition in one or more of the logical address inputs. When a transition is detected, the ATC and access rights checking circuits in the ATC initiate an address translation. Monitoring for an address transition allows the ATC to begin address translation as soon as an address is presented by the logical bus master rather than waiting for the assertion of one of the logical bus control strobes, thereby optimizing translation performance.
The control store section contains the two-level microcode store of the MC68851 and the address generation circuitry required to correctly sequence the control store during table search operations and execution of the MC68851 instruction set.
The control logic section provides residual decode for the control store and register decode outputs, and it drives control points in the execution unit (EU). The EU performs address calculations for accessing the translation tables, contains the MC68851 register set, and controls table search activities and instruction execution.
1.2.1 Coprocessor Interface
The MC68851 contains eleven coprocessor interface registers (CIRs) that are memory-mapped into the M68000 CPU space. The M68000 Family coprocessor interface is implemented asa protocol of reading and writing these registers by the main processor. The MC68020 implements this general purpose coprocessor interface protocol in hardware and microcode. The MC68851 implements a subset of the general purpose protocol.
When the MC68020 detects an MC68851 instruction, the MC68020 writes the instruction to the appropriate CIR. The register decode section decodes the access from the logical address bus ' and selects the required register in the EU. The MC68020 then reads the response CIR, which in conjunction with the control store, provides requests for any further action required of the MC68020 on behalf of the MC68851. For example, the response may request that the MC68020 fetch an operand from the evaluated effective address and transfer the operand to the operand CIR.
The only difference between a coprocessor bus transfer and any other bus transfer is that the MC68020 issues a function code and address bus encoding that indicates the CPU address space during the cycle. Thus, the memory-mapped coprocessor interface registers do not infringe upon program and data address spaces. When accessing the MC68851, the MC68020 places a coprocessor ID field of 0 (zero) onto three of the upper address lines in order to distinguish the MC68851 from other coprocessors in the system (refer to SECTION 9 COPROCESSOR INTERFACE).
Since the coprocessor interface protocol is based solely on bus transfers, it is easily emulated by software when the MC68851 is used as a peripheral with any processor capable of memory-mapped liD over an M68000-type bus.
The M68000 Family coprocessor interface is an integral part of the MC68851 and MC68020 design, with the interface tasks shared between the two. The interface is fully compatible with all present and will maintain compatibility with all future M68000 Family products. Functionality required to execute coprocessor instructions is partitioned such that the MC68020 does not have to decode coprocessor instructions, and the MC68851 does not have to duplicate main processor functions such as address calculation for data transfers.
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This partitioning provides an extension of the instruction set that permits MC68851 instructions to utilize all MC68020 addressing modes and to generate execution time exception traps. Thus, from the programmer's view, the CPU and coprocessor appear to be integrated onto a single chip. The MC68020 single-step (trace) mode is fully supported by the MC68851 and the M68000 Family coprocessor interface.The MC68851 initiates bus cycles required to search the translation tables in physical memory in order to load descriptors into the address translation cache, to check privilege information contained in the descriptors, and to maintain descriptor history information. The MC68851 does not initiate bus cycles to fetch instructions or to manipulate any data other than the descriptor operations specified above. The MC68020 is responsible for fetching instructions, transferring them to the MC68851, and performing any other actions related to these instructions with the exception of descriptor m'anipulation.
1 ;2.2 Access Level Control Interface
For operation~ initiated by the MC68020 CALLM and RTM instructions, the MC68851 can be accessed via a set of access level control registers (ALCRs) that participate in the protection mechanism supported by the MC68020 and the MC68851. Similar to the CIRs of the coprocessor interface, the ALCRs are memory-mapped into the M68000 CPU space and accesses to these registers are detected by decode logic in the BIU that selects the appropriate registers and control logic.
Refer to SECTION 10 ACCESS LEVEL CONTROL INTERFACE for further details on this interface.
1.2.3 Breakpoint Acknowledge Interface
In response to breakpoint acknowledge cycles, one final method by which the MC68851 can be accessed is via the breakpoint acknowledge interface that supports the instruction breakpoint capabilities of the MC68020. When a breakpoint acknowledge cycle in the CPU space is observed by the register decode section, the appropriate breakpoint acknowledge control and data registers are selected in the EU. The EU, under control from the control store, then provides the correct MC68851 response to the cycle.
For further information on the MC68851 breakpoint operations refer to SECTION 8 BREAKPOINTS.
1.2.4 Bus Operations
In addition to controlling access to the MC68851 from the logical bus, the BIU also contains the circuitry required to execute bus cycles in physical memory in orderto access mapping information located in the translation tables. The physical bus controller performs accesses in memory following the standard protocol of the M68000 Family bus definition.
The BIU also contains arbiters to control and/or monitor mastership of both the logical and physical buses. The MC68851 allows for multiple logical and/or physical alternate bus masters.
The bus interface of the MC68851 is described in detail in SECTION 4 BUS OPERATIONS.
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