PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
PINB – Port B Input Pins Address
PORTC – Port C Data Register
DDRC – Port C Data Direction Register
Bit 7 6 5 4 3 2 1 0
0x1B (0x3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x1A (0x3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x19 (0x39) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x18 (0x38) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x17 (0x37) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x16 (0x36) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x15 (0x35) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x14 (0x34) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PINC – Port C Input Pins Address
In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-pull Zero Output. The port pins assumes their Initial Value, even if the clock is not running. Note that the DDRC and PINC registers are available in ATmega103 compati-bility mode, and should not be used for 100% backward compaticompati-bility.
PORTD – Port D Data Register
DDRD – Port D Data Direction Register
PIND – Port D Input Pins Address
PORTE – Port E Data Register
DDRE – Port E Data Direction Register
PINE – Port E Input Pins Address
PORTF – Port F Data Register
Bit 7 6 5 4 3 2 1 0
0x13 (0x33) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x12 (0x32) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x11 (0x31) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x10 (0x30) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x03 (0x23) PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x02 (0x22) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x01 (0x21) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINF
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
(0x62) PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
DDRF – Port F Data Direction Register
PINF – Port F Input Pins Address
Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode where Port F serves as digital input only.
PORTG – Port G Data Register
DDRG – Port G Data Direction Register
PING – Port G Input Pins Address
Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR, RD and ALE).
Bit 7 6 5 4 3 2 1 0
(0x61) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x00 (0x20) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF
Read/Write R R R R R R R R
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
(0x65) – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x64) – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x63) – – – PING4 PING3 PING2 PING1 PING0 PING
Read/Write R R R R R R R R
Initial Value 0 0 0 N/A N/A N/A N/A N/A
External Interrupts
The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature pro-vides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4). When the External Interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge inter-rupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 37. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the “Electrical Characteristics” on page 328. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT Fuses as described in “Clock Systems and their Distribution” on page 37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt.
EICRA – External Interrupt Control Register A
This Register can not be reached in ATmega103 compatibility mode, but the Initial Value defines INT3:0 as low level interrupts, as in ATmega103.
• Bits 7..0 – ISC31, ISC30 - ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 48. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.
Bit 7 6 5 4 3 2 1 0
(0x6A) ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Note: 1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
EICRB – External Interrupt Control Register B
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 50. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.
Table 48. Interrupt Sense Control(1) ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Reserved
1 0 The falling edge of INTn generates asynchronously an interrupt request.
1 1 The rising edge of INTn generates asynchronously an interrupt request.
Table 49. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
tINT Minimum pulse width for asynchronous External Interrupt
50 ns
Bit 7 6 5 4 3 2 1 0
0x3A (0x5A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 50. Interrupt Sense Control(1) ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Any logical change on INTn generates an interrupt request
1 0 The falling edge between two samples of INTn generates an interrupt request.
1 1 The rising edge between two samples of INTn generates an interrupt request.
EIMSK – External Interrupt Mask Register
• Bits 7..4 – INT7 - INT0: External Interrupt Request 7 - 0 Enable
When an INT7 - INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Con-trol bits in the External Interrupt ConCon-trol Registers – EICRA and EICRB defines whether the External Interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output.
This provides a way of generating a software interrupt.
EIFR – External Interrupt Flag Register
• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in inter-nal siginter-nals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”
on page 71 for more information.
Bit 7 6 5 4 3 2 1 0
0x39 (0x59) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x38 (0x58) INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0