RAR,RAL,RTR,RTL

Certain combinations of Group I operations are common enough to be assigned separate mnemonics. These are described in Paragraph 4.3.2.2.

ROTATE1

OPERATION ROTATE POSITION IF 0,

AC AND L 2 POSITIONS

CODE.7 CLA CMA RIGHT IF 1

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CONTAINS CLL CML ROTATE IAC

OTO AC AND L

SPECIFY LEFT

GROUP 1

Figure 4-3. Group I Operate Class Instruction Format NOP No Operation

Octal code:

Operation:

7000

None. This instruction may be used to provide short delays (1.6 microseconds per instruction), or to hold a place for instructions to be inserted by the programmer.

CLA Clear Accumulator Octal code: 7200

Operation: The contents of the AC are cleared to 0000.

CLL Clear Link Octal code: 7100

Operation: The content of the Link is cleared to 0.

CMA Complement Accumulator Octal code:

Operation:

7040

The one's complement of the contents of the AC replaces the original contents of the AC.

Each bit that is 0 becomes 1, and vice versa.

CML Complement Link Octal code: 7020

Operation: The content of the Link is complemented.

!AC Increment Accumulator Octal code:

Operation:

7001

The contents of the AC are incremented by 1, using two's complement arithmetic. A carry out of bit 0 complements the Link.

RAR Rotate Accumulator Right Octal code:

Operation:

7010

The contents of the AC and Link, taken as a 13-bit register, are rotated right one position. A bit rotated out of AC_{1 1} enters the Link: the bit rotated out of the Link enters AC_{0 .} (See Figure 4-4.)

RTR Rotate Two Places Right Octal code:

Operation:

7012

The contents of the AC and Link, taken as a 13-bit register, are rotated two positions to the right. (See Figure 4-4.) This is the equivalent of two RAR instructions.

RAL Rotate Accumulator Left Octal code:

Operation:

7004

The contents of the AC and Link, taken as a 13-bit register, are rotated one place to the left. A bit leaving AC₀ enters the Link; a bit leaving the Link enters AC_{11 .} (See Figure 4-4.)

RTL Rotate Two Places Left Octal code:

Operation:

7006

The contents of the AC and Link, taken as a 13-bit register, are rotated two positions left. (See Figure 4-4.) This is equivalent to two RAL instructions.

L 0 AC 11

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0 AC 11

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Figure 4-4. Rotation Scheme for RAR, RTR, RAL, RTL

4.3.2.2 Combined Operations: Group I - The following combined operations have been given separate mnemonics

STA Set Accumulator (CLA + CMA) Octal code: 7240

Operation: Clear, then complement the AC. Resulting C(AC) = 7777.

STL Set Link (CLL + CML) Octal code: 7120

Operation: Clear, then complement the Link. Resulting C(L) = I.

CIA Complement and Increment Accumulator (CMA +!AC) Octal code: 7041

Operation: Complement the AC, then increment the result by 1. This gives the two's complement of the original C(AC). The two's complement of a number is defined as the one's complement plus 1.

GLK Get Link (CLA + RAL) Octal code: 7204

Operation: Clear the AC, then rotate one place left, thus putting the contents of the Link into AC11 . This instruction is useful in multiple precision arithmetic.

Other Useful Combinations - The programmer can place a number of selected constants in the AC by combining Group I operations as shown:

Octal Code

4.3.2.3 Operate Class: Group II - The microprogram structure of Group II operations is shown in Figure 4-5.-Any of these operations may be combined, but the programmer must be aware of the sequence of events. In addition, the sense of the skip instruction determines the manner in which combined skips are interpreted. If bit 8 is a 0, the logical OR of the tested conditions will cause a skip; if this bit is a 1, the logical AND of the conditions will cause the skip. In the first case, this means that the skip will occur if any one of the conditions tested is true; in the second case, the skip will occur only if all the conditions tested are true. The various combinations are described in Paragraph 4.3.2.4.

The sequence of events in a Group II instruction is as follows:

1. Skips 2. CLA 3. OSR

4. HL T occurs after all other specified operations have been performed.

CLA ClearAC Octal code:

Operation:

SNA DETERMINES

OPERATION OR SENSE

CODE 7 CLA s·zA OF SKIP HLT

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CONTAINS 1 SMA SNL OSR CONTAINS 0

TO SPECIFY OR OR TO SPECIFY

GROUP 2 SPA SZR OPERATE*

CLASS

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THIS BIT DISTINGUISHES GROUP D OPERATE CLASS INSTRUCTIONS FROM THE OPTIONAL EAE INSTRUCTION SET, IN WHICH THIS BIT IS SET TO 1.

Figure 4-5. Group II Operate Class Instruction Format

7600 Clear the AC SKP Skip Unconditionally Octal code: 7410

Operation: The next instruction in the program sequence is unconditionally skipped.

SNL Skip On Non-Zero Link Octal code: 7420

Skip condition: The contents of the Link equal 1.

SZL Skip On Zero Link Octal code: 7430

Skip condition: The contents of the Link equal 0.

SZA Skip On Zero Accumulator Octal code: 7440

Skip condition: The contents of the AC equal 0000.

SNA Skip On Non-Zero Accumulator Octal code: 7450

Skip condition: The contents of the AC are not equal to 0000.

SMA Skip On Minus Accumulator Octal code:

Skip condition:

7500

The contents of AC0 equal 1. By convention, a negative number is one in which the most

two's complement of such a number is its positive counterpart. In this sense, 7777 is equivalent to -1; 4000 is equivalent to -4000. The two's complement sum of a number and its two's complement is always zero.

SPA Skip On Plus Accumulator Octal code:

Skip condition:

7510

The contents of AC0 equal 0. By the convention described above, a number is positive if its most significant digit is 0.

OSR OR Switch Register With Accumulator Octal code: of the AC by the logical Inclusive OR relation; the result is left in the AC.

If either bit of a corresponding pair is set to 1, the result is 1. The result is 0 only if both AC and SR bits are 0. This instruction is normally used with CLA to obtain the actual status of the Switches (see below).

7402

The processor stops. The PC contains the address of the register following the HLT instruction.

The contents of the other processor registers are not affected.

LAS Load Accumulator From Switches (CLA + OSR) Octal code: 7604

Operation: Clear the AC, then OR the contents of the Right Switches with C(AC). This places the status of the switches in the AC. If the switch is set to 1, the corresponding AC bit is set to 1.

4.3.2.4 Combined Skips In Group II - The possible skip combinations are listed, with the conditions for a skip to occur.

If CLA is combined with any skip, the AC is cleared after the conditions have been tested.

4.3.2.5 Input/Output Transfer Class - These instructions, all of which have the basic operation code of 6000, are used to service peripheral devices, enable and disable the program interrupt, operate the memory extension control, change from 8 to LINC programming mode, and provide maintenance operations for the LINCtape subprocessor.

Most of these instructions are described in Chapter 6 with their associated devices. The program interrupt and memory extension control are discussed with their respective instructions in Paragraphs 4.4 and 4.6 of this chapter.

Mode Control - To change operating mode from 8 to LINC, the following IOT instruction is used.

LINC Switch to LINC Mode Octal code:

Execution time:

Operation:

6141 4.25 µs

Starting with the next succeeding instruction, the central processor will operate in LINC mode.

4.4 PROGRAM INTERRUPT

4.4.1 Operation

To facilitate the handling of data transfers and the checking of peripheral device status, provision is made for interrupting a program when a given condition exists. In general, an interrupt occurs when a peripheral device flag is raised (i.e., when the device is available for service, when an operation has been completed, or when a specific condition, such as an alarm, occurs within the device).

The Program Interrupt (Pl) is enabled or disabled by the program. When it is disabled, a device flag must be sensed by means of a skip; the program is not interrupted. When the interrupt is enabled, any device flag that is connected to the interrupt system will cause the following sequence of events to occur when that flag is raised:

1. The instruction in progress at the time qf the PI request is completed.

2. The contents of the program counter are stored in register 0000, and 0001 is placed in the PC.

3. Processing continues, beginning with the instruction in register 0001.

4. The PI facility is disabled.

The two IOT instructions which control the PI facility are described below.

ION Interrupt On Octal code:

Execution time:

Operation:

6001 4.25 µs

The PI facility is enabled immediately after the instruction following the ION has been executed. If a PI request is waiting at the time of the ION, the interrupt will occur after the next instruction has been completed. The enabling is delayed in this manner so that a PI service routine can return to the interrupted program before a subsequent Pl request destroys the contents of register 0000.

/OF Interrupt Off Octal code:

Execution time:

6002 4.25 µs

Operation: The PI facility is disabled. Subsequent requests will not cause a PI, although any flag causing a request may be sensed in the usual manner with an IOT skip.

4.4.2 Using the Program Interrupt

Normally, when a PI occurs, the instruction in register 0001 is a JMP to a PI service routine, which examines the expected flags to determine which device or condition caused the request. The appropriate routine is then called to service the device. During this time, the PI facility is disabled. When the device service routine is completed, control normally returns to the PI handling routine for restoring the PI facility and exiting to the main program. The last two instructions of such a routine would be:

ION /ENABLE PI FACILITY

JMP I 0 /RETURN TO MAIN PROGRAM AT THE ADDRESS

/STORED IN REGISTER 0000

The PI is not enabled until the JMP I 0 has been executed, so that the return to the main program is completed before a waiting request can cause another PI.

NOTE

Refer to Paragraph 3.3.15 for the discussion of additional aspects of Program Interrupt during LINC mode programming.

4.5 EXTENDED ARITHMETIC ELEMENT TYPE KE12 4.5.1 Operation

The Extended Arithmetic Element (EAE), Type KE 12, adds a complete automatic multiplication and division facility to the PDP-12. Programming is provided by a class of 8 mode instructions. The AC and MQ are used to accommodate full 24-bit products and dividends, and the remainder and quotient after a division. Shifting, normalizing, and register setup instructions are included. All operands are treated as unsigned integers; the programmer must establish his own sign conventions. The normalizing instruction facilitates the writing of floating-point subroutines.

4.5.2 EAE Instructions

The EAE instruction set has a basic operation code of 7401; some functions are microprogrammable, as in Operate Class instructions. The microprogram structure of the EAE class is shown in Figure 4-6.

CONTAINS 1 TO

OPERATION SPECIFY

CODE 74 MQA MQL EAE GROUP

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Figure 4-6. EAE Instruction Format

As with other microprogrammed instructions, EAE operations are performed in a given order. Operations can be combined in a single instruction, except that operations occurring at the same time cannot be combined with meaningful results.

The order of events is as follows:

1. CLA

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