Division - Division is performed as follows:

1. Load the least significant 12 bits of the dividend into the AC using the TAD instruction, then transfer the contents of the AC into the MQ using the MQL command.

2. Load the most significant 12 bits of the dividend into the AC.

3. Give the DVI command.

The 24-bit dividend contained in the AC and MQ is divided by the 12-bit divisor contained in the next successive core memory location (p + 1). This operation takes a maximum of 10.0 microseconds; when complete, a 12-bit quotient is held in the MQ, the 12-bit remainder is in the AC, and the Link holds a 0 if divide overflow did not occur. To prevent divide overflow, the divisor in the core memory must be greater than the 12 bits of the dividend held in the AC. When divide overflow occurs, the Link is set and the division is concluded after only one_ cycle.

Therefore, the instruction following the divisor in core memory should be an SZL microinstruction to test for overflow. The instruction following the SZL may be a jump to a subroutine that services the overflow. This subroutine may cause the program to type out an error indication, rescale the divisor or the dividend, or perform other mathematical corrections, then repeat the divide routine.

The following program examples demonstrate the use of the EAE in division.

a. Division of 24-Bit Unsigned Numbers

Enter with the low order 12 bits of the dividend in the AC and the high order 12 bits of the dividend in memory location labeled HIGH 12. The divisor is in memory location labeled DIVISOR upon entry. Exit with the quotient in the AC and the remainder in location labeled REMAIN.

CLL MQL

TAD HIGH 12 DVI

DIVISOR, (12 BIT DIVISOR HERE) SZL

JMP EXIT DCAREMAIN MQA

/CLEAR LINK FOR OVERFLOW CHECK.

/LOAD MQ WITH LOW ORDER DIVIDEND /LOAD AC WITH HIGH ORDER DIVIDEND /INITIATE DIVIDE

/OVERFLOW?

/YES - EXIT

/NO - STORE REMAINDER /AND LOAD AC WITH QUOTIENT b. Division of 24-Bit Signed Numbers

Enter with the low order 12 bits of the dividend in memory location labeled LOW 12 and the high order 12 bits of the dividend in memory location labeled HIGH 12. The 12 bit divisor is in location labeled DIVISOR. Exit with the unsigned remainder in location labeled REMAIN, and the signed quotient in the AC.

CLA CLI TAD HIGH 12 SMA CLA JMP .+12 TAD LOW 12 CMA IAC DCA LOW 12

/CLEAR AC AND LINK

/LOAD AC WITH HIGH 0RDER DlVIDEND /DIVIDEND NEGATIVE?

/NO - SKIP NEGATION

/YES - LOAD AC WITH LOW ORDER DIVIDEND /NEGATE IT AND

/STORE IT BACK

CMA

DIVISOR, (DIVISOR STORED HERE) SZL

/YES - INCREMENT HIGH ORDER /AND STORE IT BACK

/CHECK LINK FOR SIGN OF RESULT /POSITIVE - STORE -1 IN SIGN /NEGATIVE - STORE 0 IN SIGN /GET LOW ORDER DIVIDEND /STORE IT IN MQ

/LOAD AC WITH HIGH ORDER DIVIDEND /DIVIDE

/OVERFLOW?

/YES - EXIT ON OVERFLOW

/NO - STORE UNSIGNED REMAINDER /LOAD AC WITH QUOTIENT

/SHOULD QUOTIENT BE NEGATIVE?

/YES - NEGATE IT

When additional 4096-word memory banks are attached to the PDP-12, the Memory Extension Control provides access to the additional storage, both for programs and data. The registers of the Control are already built into the PDP-12; they are described in Paragraph 3.3.15 in relation to LINC mode memory control. In the 8 mode, the functions of these registers are the same, but only a portion of each register is used. The Instruction Field (IF), Data Field (DF), and Instruction Field Buffer (IB) registers are each five bits long; the two low-order bits of the 5-bit total pertain only to LINC mode programming operations. In 8 mode the Save Field register (Interrupt Buffer) uses only six bits; the four low-order bits are unused.

4.6.1 Registers

4.6.1. l Instruction Field Register (IF), 3 Bits - These three bits serve as an extension of the PC for determining the 4096-word field from which executable instructions are to be taken. All direct memory references are made to registers in the Instruction Field. With one exception, all JMP and JMS instructions, whether direct or indirect, are to registers within the Instruction Field. The exception is the first JMP or JMS executed after a CIF instruction is given. This causes the field to change.

4.6.1.2 Data Field Register (OF), 3 Bits - These three bits serve as an extension of the Memory Address register for determining which memory field contains the operands to be accessed by the memory reference instructions AND, TAD, DCA, and ISZ when indirect addressing is used. The Data Field and Instruction Field may be set to the same field.

4.6.1.3 Instruction Field Buffer (IB), 3 Bits - This serves as an input buffer for the IF. Except for a direct transfer from the console switches, all transfers into the IF must pass through the IB. When a CIF or RMF instruction is executed, information going to the IF is first placed in the IB. At the next occurrence of a JMP or JMS, the contents of the IB are transferred to the Instruction Field register, and programming continues in the. new field, starting in the target register ·of the jump.

4.6.1.4 Save Field Register (SF), 6 Bits - Also called the Interrupt Buffer. When a program interrupt occurs, the contents of the IF and DF are stored in the Save Field register, as shown in Figure 4-10. After the PI has been serviced, an RMF instruction will cause the contents of the SF to be restored to the DF and IB. The SF can be examined by using the RIB instruction.

4.6.1.5 Break Field Register (BF), 3 Bits - When an external device requires extended memory for the transfer of data using the Data Break Facility, the contents of the BF specify the memory field to be accessed.

4.6.2 Instructions

All Extended Memory IOT instructions require 4.3 microseconds for execution.

--- --,

..._ _ _ _ _ _ _ - - - - .J I

I

'--...--....----... ----T-...,i--' - - - - .J

r---1

L - - - - - - - - - - - - - - L--.&....--"--..._ _ __._ _ __. _ _ _ AC

12-0113

Figure 4-10. Data Path to SF and AC CDF Change Data Field

Octal code:

Operation:

62Nl, ^O~N~7

The quantity N is transferred to the Data Field register. All subsequent indirect memory references by AND, TAD, ISZ, and DCA are to the new field.

CIF Change.Instruction Field Octal code:

Operation:

62N2, ^{O~N ~7}

The quantity N is transferred to the Instruction Field Buffer. At the occurrence of the next JMP or JMS instruction, whether direct or indirect, the contents of the IB are transferred to the IF. The effective address of the jump is placed in the PC, and the program continues from that address in the new Instruction Field.

In both CIF and CDF, the number N occupies bits 6-8 of the instruction code.

RDF Read Data Field Octal code:

Operation:

6214

The contents of the Data Field register are ORed into AC_{6 _8 •} The other bits of the AC are unaffected.

RIF Read Instruction Field Octal code:

Operation:

6224

The contents of the Instruction Field register are ORed into AC_{6 - 8 •} The other bits of the AC are unaffected.

RIB Read Interrupt Buffer Octal code: 6234

Operation: The contents of the Save Field register (Interrupt Buffer) are transferred to the AC, as follows:

Bits 0-2 (IF) are ORed into AC_{6 - 8 ;} bits 3-5 (DF) are ORed into AC_{9 - 11 .} RMF Restore Memory Field

Octal code:

Operation:

6244

The contents of the Save Field register are placed in the Instruction Field Buffer and DF as follows: Bits 0-2 (original Instruction Field) are transferred to the IB; bits 3-5 (original Data Field) are restored to the Data Field register. This instruction is used to restore the Memory Field registers after a program interrupt has been serviced. Normally, the next instruction after the RMF would be JMP I 0; the address of the interrupted program, stored in register 0000 of field 0, is placed in the PC, and the contents of the IB are placed in the Instruction Field register; the program thus returns to the main program with the Memory Fields restored to their original values.

4.6.3 Programming

All instructions, effective addresses, and directly-addressed operands are taken from the field specified by the contents of the Instruction Field Register. All indirectly-addressed operands are taken from (or are stored in) the field specified by the contents of the Data Field Register. The following chart shows the results of the four possible addressing combinations, when the IF and DF designate different memory fields.

Instruction Bits Indirect Page

0 0

0

0

Fields IF DF

m n

m n m n

m n

Effective Address

The operand is in Page 0 of Field m at the address specified by instruction bits 5-11.

The operand is in the current page of Field m.

The effective address of the operand is in Page 0 of Field m at the location specified by instruction bits 5-11. The operand is in Field n, in the location specified by the contents of the effective address.

The effective address is taken from the current page of Field m, at the location specified by instruction bits 5-11. The operand is in Field n, in the location specified by the contents of the effective address.

4.6.3. l Autoindexing - When any memory field is used as an Instruction Field, registers 10-17 of that field have autoindexing properties, just as the corresponding locations in field 0 do. This is necessary so that a program can operate correctly regardless of the actual memory field assigned by the IF. When an autoindex register is indirectly addressed, the resulting effective address is used to obtain the operand from the Data Field specified by the DF.

Example:

C(IF)

=

2.

In field 4:

In field 2:

C(DF) = 4.

C(4326)

=

¹¹⁰⁷

C(OOl 2)

=

4325

C(AC)

=

0.

The instruction TAD I 12 is executed in field 2.

C(0012) + 1-+ C(0012). Resulting effective address is 4326.

C(4326) in field 4 are added to the AC.

C(AC)

=

1107 when the instruction is completed.

4.6.3.2 Calling A Subroutine Across Fields - The problem is to let the subroutine know which field contains the calling program, so that it can return to the proper point wheJ.1 it's finished. This is most easily done by setting the DF to the same field as the IF, then setting the IF to the field containing the subroutine, an<l executing a JMS to read the subroutine. The subroutme uses the DF to indirectly obtain data from the calling field, then transfers the C(DF) back to the IF Buffer to return to the calling program. The following example shows a general procedure for doing this.

/CALLING PROGRAM IN FIELD 2, SUBROUTINE IN FIELD 4 /CURRENT DATA FIELD IS 1

/CALLING SEQUENCE SAVES CURRENT DF, PUTS IF IN DF, CALLS /SUBROUTINE. ON RETURN, ORIGINAL DF IS RESTORED

CLA

TAD KCDF /CDF INSTRUCTION TO AC

RDF /C(DF) TO AC 6-8 FORMS CDF 10 (6211)

DCA RESDF /STORE IN SEQUENCE TO RESTORE DF

TAD KCDF /CDFTOAC

RIF /C(IF) TO AC 6-8 FORMS CDF 20 (6221)

DCA SETDF /STORE IN SEQUENCE TO SET DF

SETDF, 0000 /SETS DF TO CURRENT IF

CIF 40 /SET IF BUFFER TO SUBROUTINE FIELD 4

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