CHAPTER 4 8 MODE PROGRAMMING
4.1 ORGANIZATION OF MEMORY
4.1.1 Organization
In the 8 mode, the basic 4096-word memory is divided into 32 pages of 128 words each for addressing purposes Within one of these pages, operands may be addressed directly by memory reference instructions. Access to operands across page boundaries (except for Page 0) requires indirect addressing.
Executable programs may be stored in any page of memory, and program sequences may extend across several pages. The program counter is indexed over all 12 bits in the 8 mode, so that a straight-line program sequence will pass from the last word of a page to the first word of the next. A programmed jump across page boundaries, however, requires an indirect reference. The organization of one memory field in 8 mode is shown in Figure 4-1.
4.1.2 Page 0
The first page of memory (addresses 000-177) contains several registers reserved for special use, which the .programmer must take into account. These are:
Address 0000 0001 0010-0017
Use
During a program interrupt, holds C(PC).
Contains the first instruction to be executed after a program interrupt.
Automatic index registers (see Paragraph 4.2.2).
4.1.3 Extended Memory
PAGE (OCTAL) ADDRESSES 0
Figure 4-1. Organization of Memory, 8 Mode
Additional 4K memory fields are organized in the same manner as the basic field. The Memory Field registers determine the assignment of fields (see Paragraph 4.6).
4.2 MEMORY ADDRESSING METHODS
4.2.1 Direct Addressing
Note that only seven bits (5-11) are available for use as an address. This is just sufficient to give access to 128 registers, or exactly one page. The state of bit 4 of the instruction determines which of two possible pages the 7-bit page address references. If this bit is 1, the page address is on the current page; that is, the one in which the instruction itself is stored. If bit 4 is 0, the page address is on Page 0. Thus, a memory reference instruction has direct access to a total of 256 registers of memory; the 128 locations of Page 0, and those of the current page.
Examples:
To store the contents of the AC in register 150 of the current page:
DCA 350 Octal code: 3350. The page address is 150; bit 4 (Page bit) set to 1 gives a total octal value of 350 for the address.
To store the contents of the AC in register 150 of Page 0:
DCA 150 Octal code: 3150. With the page bit set to 0, the complete octal address is 150.
As one can see from these examples, it is useful to think of page addresses running from 000-1 77 on Page 0, and from 200-377 on the current page.
4.2.2 Indirect Addressing
To gain access to registers outside of Page 0 or the current page, indirect addressing must be used. If bit 3 of a mem-ory reference instruction is set to 1 (see Figure 4-2), the contents of the register designated by bits 5-11 are taken as the "effective" address of the operand. This is a full 12-bit number which gives the absolute address of any reg-ister in the 4K memory field.
OPERATION MEMORY
CODE PAGE
I A
'\ ,-A-..
0 2 3
I
4I
~ 6 7 8 9 10 11'--y-J
INDIRECT PAGE
ADDRESSING ADDRESS
12-0122
Figure 4-2. Memory Reference Instruction Format
In the following examples, as in normal 8 mode programming, the letter I is used as a mnemonic to represent the presence of a 1 in bit 3.
Examples:
a. To store the contents of the AC in register 100 of page 10 (absolute address 2100), using an effective address stored on the current page:
Absolute Address 0410 0500
Contents DCA I 300 2100
Action /OCTAL CODE: 3700. THE /EFFECTIVE ADDRESS IS /CONTAINED IN REGISTER 500, /(PAGE ADDRESS 300)
b. To store the C(AC) in register 2100, using an effective address stored in Page 0:
Absolute Address 0050 0410
Bit 3 0
0
4.2.3 Autoindexing
Contents 2100 DCA I 50
Action
/EFFECTIVE ADDRESS, STORED /ON PAGE 0
/OCTAL CODE: 3450. (BIT 4
=
0) Table 4-1. Summary of Addressing Methods in 8 ModeBit 4
0
0
Effective Address
The operand is in Page 0 at the address specified by bits 5 through 11.
The operand is in the current page at the address specified by bits 5 through 11.
The absolute address of the operand is taken from the contents of the location in Page 0 designated by bits 5 through 11.
The absolute address of the operand is taken from the contents of the location in the current page designated by bits 5 through 11.
The eight registers in locations 10-17 of Page 0 have a special function when indirectly addressed. The contents of such a register are first incremented by 1; the result is taken as the effective address of the operand. This autoindexing feature allows the programmer to address a series of contiguous locations without extra address
Example:
To obtain the sum of 100 numbers stored in registers 1000-1077.
Address /DEPOSIT IN AUTOINDEX REGISTER 10. (CLEARS AC) /PUT-100 IN AC (COUNT OF ADDENDS IN TABLE) /DEPOSIT IN REGISTER FOR COUNTING
/C( 10) INCREMENTED BY 1, THEN USED AS
/EFFECTIVE ADDRESS TO GET ADDEND FROM TABLE /INCREMENT COUNT. IF RESULT IS 0000, SKIP
/THE NEXT INSTRUCTION.
/IF NOT FINISHED, GO BACK TO GET NEXT ADDEND /WHEN FINISHED, STOP; AC CONTAINS THE SUM /ADDRESS-I OF TABLE OF ADDENDS
/COUNT OF TABLES ENTRIES
/HOLDS COUNT DURING EXECUTION OF PROGRAM When register 10 is first accessed, its contents are incremented from 777 to 1000, then used as the effective address to obtain the first addend. The next time around the loop, C( 10) is again incremented by 1, to 1001, for the next operand. At the end of the sequence, C( 10)
=
1077.4.3 8 MODE INSTRUCTIONS (See Appendix B) 4.3.1 Memory Reference Instructions
There are six memory reference instructions: DCA, TAD, AND, ISZ, JMP, and JMS. All may use either direct or indirect addressing. When indirect addressing is specified, 1.6 microseconds is added to the execution time.
DCA Deposit and Clear Accumulator Form:
TAD Two's Complement Add to Accumulator Form: previous contents of the AC are lost; the contents of Y are not changed. ·
AND Logical AND to Accumulator Form:
Octal code:
Execution time:
Operation:
AND Y 0000 + y 3.2 µs
The contents of the AC and the contents of Y are combined according to the Boolean AND relation, with the result left in the AC. The operation is performed on corresponding bits of each operand, independent of the other bits in the two operands. The truth table for the AND relation is shown below:
0
0
·~
I
0 1When corresponding bits of AC and Y are both 1, the result is 1. Otherwise, the result is 0. The previous C(AC) are lost; the C(Y) are unchanged.
ISZ Increment And Skip If Zero Form:
Octal code:
Execution time:
Operation:
JMP Jump Form:
Octal code:
Execution time:
Operation:
ISZ Y 2000 + y 3.2 µs
The contents of Y are incremented by 1. If the result is 0000, the next instruction in sequence is skipped; otherwise, the next instruction is executed. The contents of the AC are not affected.
JMP Y 5000 + y 1.6 µs
The address Y is placed in the PC, and the next instruction is taken from register Y; the program continues from that point. The contents of the AC are not affected.
JMS Jump to Subroutine Form:
Octal code:
Execution time:
Operation:
JMS Y 4000+Y 3.2 µs
The contents of the PC are stored in Y. The address Y + 1 is placed in the PC, and the program continues from Y + 1. The contents of the AC are not affected. To return from the subroutine to the point at which the JMS was given (i.e., to the register immediately following the JMS), the instruction JMP I Y is executed. The contents of Y are taken as the effective address;
since Y contains the PC stored at the time of the JMS, control returns to the calling program.
4.3.2 Operate Class Instructions
This class is divided into two groups, I and II. Group I instructions include miscellaneous operations on the
Operate class instructions are microprogrammable; they may be combined to provide several operations within a single instruction. However, combinations can be made only within a group; operations from different groups cannot be combined. To ease this restriction, the operation CLA (Clear the AC) is available in both groups. All Operate Class instructions require 1.6 microseconds for execution.
4.3.2.1 Operate Class: Group I - The microprogram structure of Group I instructions is shown in Figure 4-3. Any combination of these functions can be made, but the programmer must be aware of the order in which the operations are performed when the instruction is executed. This order is as follows:
1. CLA, CLL 2. CMA,CML 3. IAC