A complete description of the GCSR is provided in the following tables. Each register definition includes a table with 5 lines:
❏ Line 1 is the base address of the register as viewed from the local bus and as viewed from the VMEbus, and the number of bits defined in the table.
❏ Line 2 shows the bits defined by this table.
❏ Line 3 defines the name of the register or the name of the bits in the register.
❏ Line 4 defines the operations possible on the register bits as follows:
R This bit is a read-only status bit.
R/W This bit is readable and writable.
S/R Writing a one to this bit sets it. Reading it returns its current status.
2
❏ Line 5 defines the state of the bit following a reset as defined below:A summary of the GCSR is shown in Table 2-4.
Table 2-4. VMEchip2 Memory Map (GCSR Summary) P This bit is affected by power-up reset.
S The bit is affected by SYSRESET.
L The bit is affected by local bus reset.
X The bit is not affected by reset.
Offsets
VME-bus Local
Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 CHIP REVISION CHIP ID
2 4 LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0 RST ISF BF SCON SYSFL X X X 4 8 GENERAL PURPOSE CONTROL AND STATUS REGISTER 0
6 C GENERAL PURPOSE CONTROL AND STATUS REGISTER 1
8 10 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2
A 14 GENERAL PURPOSE CONTROL AND STATUS REGISTER 3
C 18 GENERAL PURPOSE CONTROL AND STATUS REGISTER 4
E 1C GENERAL PURPOSE CONTROL AND STATUS REGISTER 5
VMEchip2 Revision Register
2
This register is the VMEchip2 revision register. The revision level for the VMEchip2 starts at zero and is incremented if mask changes are required.
VMEchip2 ID Register
This register is the VMEchip2 ID register. The ID for the VMEchip2 is 10.
VMEchip2 LM/SIG Register
This register is the VMEchip2 location monitor register and the interrupt register.
ADR/SIZ Local bus: BASE+0100/VMEbus: $XXY0 (8 bits)
BIT 15 . . . 8
NAME VMEchip2 Revision Register
OPER R
RESET 01 PS
ADR/SIZ Local bus: BASE+0100/VMEbus: $XXY0 (8 bits)
BIT 7 . . . 0
NAME VMEchip2 ID Register
OPER R
RESET 10 PS
ADR/SIZ Local bus: BASE+0104/VMEbus: $XXY2 (8 bits)
BIT 15 14 13 12 11 10 9 8
NAME LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0
OPER R R R R S/R S/R S/R S/R
RESET 1 PS 1 PS 1 PS 1 PS 0 PS 0 PS 0 PS 0 PS
2
SIG0 The SIG0 bit is set when a VMEbus master writes a one to it. When the SIG0 bit is set, an interrupt is sent to the local bus interrupter.The SIG0 bit is cleared when the local processor writes a one to the SIG0 bit in this register or the CSIG0 bit in the local interrupt clear register.
SIG1 The SIG1 bit is set when a VMEbus master writes a one to it. When the SIG1 bit is set, an interrupt is sent to the local bus interrupter.
The SIG1 bit is cleared when the local processor writes a one to the SIG1 bit in this register or the CSIG1 bit in the local interrupt clear register.
SIG2 The SIG2 bit is set when a VMEbus master writes a one to it. When the SIG2 bit is set, an interrupt is sent to the local bus interrupter.
The SIG2 bit is cleared when the local processor writes a one to the SIG2 bit in this register or the CSIG2 bit in the local interrupt clear register.
SIG3 The SIG3 bit is set when a VMEbus master writes a one to it. When the SIG3 bit is set, an interrupt is sent to the local bus interrupter.
The SIG3 bit is cleared when the local processor writes a one to the SIG3 bit in this register or the CSIG3 bit in the local interrupt clear register.
LM0 This bit is cleared by an LM0 cycle on the VMEbus. When this bit is cleared, an interrupt is set to the local bus interrupter. This bit is set when the local processor or a VMEbus master writes a one to the LM0 bit in this register or the CLM0 bit in local interrupt clear register.
LM1 This bit is cleared by an LM1 cycle on the VMEbus. When this bit is cleared, an interrupt is set to the local bus interrupter. This bit is set when the local processor or a VMEbus master writes a one to the LM1 bit in this register or the CLM1 bit in local interrupt clear register.
LM2 This bit is cleared by an LM2 cycle on the VMEbus. This bit is set when the local processor or a VMEbus master writes a one to the LM0 bit in this register.
LM3 This bit is cleared by an LM3 cycle on the VMEbus. This bit is set when the local processor or a VMEbus master writes a one to the LM3 bit in this register.
VMEchip2 Board Status/Control Register
2
This register is the VMEchip2 board status/control register.
SYSFL This bit is set when the VMEchip2 is driving the SYSFAIL signal.
SCON This bit is set if the VMEchip2 is system controller.
BF When this bit is high, the Board Fail signal is active. When this bit is low, the Board Fail signal is inactive. When this bit is set, the VMEchip2 drives SYSFAIL if the inhibit SYSFAIL bit is not set.
ISF When this bit is set, the VMEchip2 is prevented from driving the VMEbus SYSFAIL signal line. When this bit is cleared, the VMEchip2 is allowed to drive the VMEbus SYSFAIL signal line.
RST This bit allows a VMEbus master to reset the local bus. Refer to the note on local reset in the GCSR Programming Model section, earlier in this chapter. When this bit is set, a local bus reset is generated.
This bit is cleared by the local bus reset.
General Purpose Register 0
This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
ADR/SIZ Local bus: BASE+0104/VMEbus: $XXY2 (8 bits [5 used])
BIT 7 6 5 4 3 2 1 0
NAME RST ISF BF SCON SYSFL
OPER S/R R/W R R R
RESET 0 PSL 0 PSL 1 PS X 1 PSL
ADR/SIZ Local bus: BASE+0108/VMEbus: $XXY4 (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 0
OPER R/W
RESET 0 PS
2
General Purpose Register 1This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
General Purpose Register 2
This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
ADR/SIZ Local bus: BASE+010C/VMEbus: $XXY6 (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 1
OPER R/W
RESET 0 PS
ADR/SIZ Local bus: BASE+0110/VMEbus: $XXY8 (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 2
OPER R/W
RESET 0 PS
General Purpose Register 3
2
This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
General Purpose Register 4
This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
ADR/SIZ Local bus: BASE+0114/VMEbus: $XXYA (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 3
OPER R/W
RESET 0 PS
ADR/SIZ Local bus: BASE+0118/VMEbus: $XXYC (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 4
OPER R/W
RESET 0 PS
2
General Purpose Register 5This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification.
ADR/SIZ Local bus: BASE+011C/VMEbus: $XXYE (16 bits)
BIT 15 . . . 0
NAME General Purpose Register 5
OPER R/W
RESET 0 PS
3
Introduction
This chapter defines the VME2PCI, PCI local bus to VMEbus interface chip.
There are four internal standard buses on the
MVME1603/MVME1604: PowerPC 603/604 Processor bus, PCI Local Bus, ISA Bus, and Ô040bus (VMEchip2Õs local bus). The MPC105 PCI Bridge/Memory Controller provides the interface from the processor bus to PCI. The S82378ZB device performs the bridge function between PCI and ISA. Two ASIC devices
(VME2PCI and VMEchip2) are used to interface the PCI Local Bus to Ô040bus.