The CSR on MVME1603/MVME1604 consists of: the CPU
Configuration Register, the Software Readeable Header, the Board Configuration Register, and the DRAM Size Register. These registers are accessible in ISA I/O space.
Note that in the OPER row, R = read only bit, R/W = read or write bit, and W = write only bit.
Table 1-4. PCI View of the PCI Memory Map
PCI Address
Size
Processor Bus Address
Definition Notes
Start End Start End
00000000 00FFFFFF 16M Not forwarded to MPU bus PCI/ISA Memory Space 1, 2 01000000 7FFFFFFF 1G - 16M Not forwarded to MPU bus PCI Memory Space 2 80000000 FFFFFFFF 2G 00000000 7FFFFFFF Onboard DRAM (via MPC105)
00000000 FFFFFFFF 4G Not forwarded to MPU bus PCI/ISA I/O Space
CPU Configuration Register
The CPU Configuration Register provides the configuration information about the PM603/PM604 module.This register resides on the PM603/PM604 mezzanine module, but actual decoding is done by the MVME160X board.
L2P1-L2P0 L2 Cache Present. These bits are defined as follows:
CKM1-CKM0Clocking Configuration. These bits reflect the clocking configuration of the PM603/PM604. The encoding for these bits is as follows:
CPUTYPE CPU Type. These four bits reflect the CPU type information. For the PM603/PM604, this field is hardwired to 0001 (binary).
REG CPU Configuration Register - 0800 (hex)
BIT SD7 SD6 SD5 SD4 SD3 DS2 SD1 SD0
FIELD CPUTYPE CKM1 CKM0 L2P1 L2P0
OPER R R R R R
RESE T
0001 (binary) N/A N/A N/A N/A
L2P1 L2P0 L2 Cache Size
0 0 512KB
0 1 256KB
1 0 1MB
1 1 L2 Cache Not Present
CKM1 CKM0 PCI Bus Clock CPU External Bus Clock
0 0 33MHz 33MHz
0 1 20MHz 40MHz
1 0 25MHz 50MHz
1 1 33MHz 66MHz
Software Readable Header J8 or J14
A 2x8 header is provided as the Software Readable Header (SRH).
A logic 0 means a jumper is installed for that particular bit and a logic 1 means the jumper is not installed. SRH Bit 0 is associated with Pin 1 and Pin 2 of the SRH, and SRH Bit 7 is associated with Pin 15 and Pin 16 of the SRH. The SRH is a read-only register located at ISA I/O address x801 (hex).This register is J8 on the MVME1600-001 main module, but it is J14 on the MVME1600-011 main module. The default (as shipped) configuration is with the first four jumpers, SRH0 through SRH3, installed. They are used by the debug monitor, PPCBug .
REG Software Readable Header Register - 0801 (hex)
BIT SD7 SD6 SD5 SD4 SD3 DS2 SD1 SD0
FIELD SRH7 SRH6 SRH5 SRH4 SRH3 SRH2 SRH1 SRH0
OPER R R R R R R R R
RESE T
N/A N/A N/A N/A N/A N/A N/A N/A
J8 or J14
2 SRH7 SRH6 SRH5
SRH1 SRH4 SRH3 SRH2
16 15
1 SRH0
USER-DEFINABLE USER-DEFINABLE USER-DEFINABLE
USE DEFAULT CONFIGURATION PARAMETERS (IN DIAGNOSTICS) USER-DEFINABLE
RESERVED FOR FUTURE USE
VIDEO ENABLE (IN=COM1 SERIAL PORT; OUT=VGA PORT)
RESERVED FOR FUTURE USE PPC1Bug INSTALLED
8 7
Board Configuration Register
The Board Configuration Register is an 8-bit register providing the configuration information about the MVME1603/MVME1604 Single Board Computer. This read-only register is located at located at ISA I/O address x0F02. This register is on the MVME1600-001 main module
GIOP_ MVME760 module Present. If set, MVME760 transition module is not connected. If cleared, MVME760 module is connected. (This applies only to MVME1600-00x boards, NOT MVME1600-0xx.) SCCP_ Z85230 ESCC Present. If set, there is no on-board
sync serial support (ESCC not present). If cleared, there is on-board support for sync serial interface via Z85230 ESCC.
PMCP_ PMC Present. If set, there is no PCI Mezzanine Card installed in the PMC Slot. If cleared, the PMC slot contains a PMC.
VMEP_ VMEbus Present. If set, there is no VMEbus
interface. If cleared, VMEbus interface is supported.
GFXP_ Graphics Present. If set, there is no onboard graphics interface. If cleared, there is an onboard graphics capability (MVME1600-0xx has no graphics).
LANP_ Ethernet Present. If set, there is no Ethernet transceiver interface. If cleared, there is on-board Ethernet support.
REG Board Configuration Register - 0802 (hex)
BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD GIOP_ SCCP_ PMCP_ VMEP_ GFXP_ LANP_ SCSIP_
OPER R R R R R R R R
RESE T
N/A N/A 1 N/A N/A N/A N/A N/A
SCSIP_ SCSI Present. If set, there is no on-board SCSI interface. If cleared, on-board SCSI is supported.
DRAM Size Register
The DRAM Size Register is an 8-bit register providing the DRAM size information. Banks 0 and 1 are on the PM603/PM604; Banks 2 and 3 reside on the RAM104 DRAM Add-on module. This register resides on the PM603/PM604 module but the actual address decoding is done by the MVME160X board.
SIZ2-SIZ0 DRAM Size. These bits provide the DRAM size information for the four banks of DRAM supported by the PM603/PM604. The encoding for these size bits is as follows:
REG DRAM Size Register - 0804h
BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD B2/B3 ASYM_
B2/B3 SIZ2
B2/B3 SIZ1
B2/B3 SIZ0
B0/B1 ASYM_
B0/B1 SIZ2
B0/B1 SIZ1
B0/B1 SIZ0
OPER R R R R R R R R
RESE T
N/A N/A N/A N/A N/A N/A N/A N/A
B0/B1 (B2/B3) DRAM Size
SIZ2 SIZ1 SIZ0 Bank 0 (Bank 2) Bank 1 (Bank 3)
0 1 1 Not Present Not Present
0 1 0 8 MB Not Present
0 0 1 32 MB Not Present
0 0 0 128MB Not Present
1 1 1 Not Present Not Present
1 1 0 8 MB 8 MB
1 0 1 32 MB 32 MB
1 0 0 128 MB 128 MB
ASYM_ Asymmetric Refresh Mode. When cleared, this bit indicates that the DRAM devices installed for Bank 0 and Bank 1 (Bank 2 and Bank 3) have more row address bits than column address bits. This bit is used to determine how to program the MPC105 chip appropriately. Note that, at this time, only the 4M x 4 DRAM devices (32MB banks) have this option. For 4M x4 DRAM, the asymmetric refresh mode is also referred to as the 4K refresh mode. For these devices, there would be 12 row addresses and 10 column addresses.