If multiple masters are connected to the same bus, transmissions may be initiated simul-taneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the trans-fer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver.
Figure 95. An Arbitration Example
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from Master to Slave Transmitted from Slave to Master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
Device n
SDA
SCL
... R1 R2
VCC
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same slave.
In this case, neither the slave nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are being addressed by the winning master. If
addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.
This is summarized in Figure 96. Possible status values are given in circles.
Figure 96. Possible Status Codes Caused by Arbitration
Own Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
Read
B0 68/78 38 SLA
START Data STOP
Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When the voltage on the posinega-tive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-gram of the comparator and its surrounding logic is shown in Figure 97.Figure 97. Analog Comparator Block Diagram(2)
Notes: 1. See Table 80 on page 200.
2. Refer to Figure 1 on page 2 and Table 25 on page 57 for Analog Comparator pin placement.
Special Function IO Register – SFIOR
• Bit 3 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 200.
ACBG BANDGAP REFERENCE
ADC MULTIPLEXER OUTPUT ACME ADEN
(1)
Bit 7 6 5 4 3 2 1 0
ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 SFIOR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Analog Comparator Control and Status Register – ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off.
This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and Idle mode. When changing the ACD bit, the Analog Compar-ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 41.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-ing the correspondexecut-ing interrupt handlexecut-ing vector. Alternatively, ACI is cleared by writexecut-ing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-log Comparator Interrupt is activated. When written Ana-logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.
Bit 7 6 5 4 3 2 1 0
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator inter-rupt. The different settings are shown in Table 79.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.