R2 C
632 kll 50 pF
II
I
MC68HC05P1
POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °C can be obtained from:
where:
TA 6JA Po PINT PliO
TJ=TA+(PO·eJA) (1)
= Ambient Temperature, °c
= Package Thermal Resistance, Junction-to-Ambient, °CIW
= PINT+PI/O
= ICC x VCC' Watts - Chip Internal Power
= Power Oissipation on Input and Output Pins - User Oetermined
DC ELECTRICAL CHARACTERISTICS
For most applications PI/O<PINT and can be neglected.
The following is an approximate relationship between Po and T J (if PliO is neglected):
PO=K..:..(TJ+273°C) (2)
Solving equations (1) and (2) for K gives:
K = PO· (T A + 273°C) + IlJA"P02 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Po (at equilibrium) for a known T A' Using this value of K, the values of Po and T J can be obtained by solving equa-tions (1) and (2) iteratively for any value of T A.
(VOO = 5.0 Vdc:!:: 10%, VSS =0 Vdc, TA =TL to TH, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Output Voltage, I Load'-;; 1 0 0 f.LA VOL
- -
0.1 VVOH VOO-0.1
-
-Output High Voltage (see Figure 13) VOH V
(lLoad = 0.8 rnA) PA7-PAO, PB7-PB5, PC7-PCO, P05, TCMP VOO-0.8
-
-Output Low Voltage (see Figure 14) VOL
- -
04 V(lLoad = 1.6 rnA) PA7-PAO, PB7-PB5, PC7-PCO, P05, TCMP
Input High Voltage VIH 0.7 xVOO - VOO V
PA7-PAD, PB7-PB5. PC7-PCO, P05. P07ITCAP, IRQ.
RESET, OSC1
Input Low Voltage VIL VSS
-
0.2x VOO VPA7-PAD, PB7-PB5, PC7-PCO, P05, P07/TCAP, IRQ, RESET, OSC1
Oata Retention Mode (00 to 70°C) VRM 2.0
- -
VSupply Current (see Notes) 100
Run (see Figures 15 and 16)
-
3.5 7.0 mAWalt (see Figures 15 and 16)
-
1.6 4.0 'mAStop (see Figure 16)
25°C
-
2.0 50 f.LA0° to 70°C (Standard)
-
- 140 f.LA1/0 Ports Hi-Z Leakage Current IlL
-
- :!::10 f.LAPA7-PAO,PB7-PB5, PC7-PCO, P05
Input Current lin
- -
:!::1 f.LARESET, IRQ, OSC1, P05, P07/TCAP
Capacitance pF
Ports (as Input or Output) Cout
- -
12RESET, IRQ, P05, P07/TCAP Cln
- -
8NOTES.
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range. 25°C only.
3. Run (Operating) 100, Wait 100: Measured usrng external square wave clock source (fosc = 4.2 MHz)' all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop 100: All ports configured as inputs, VIL = 0.2 V, VIH = VOO - 0.2 V.
5. Stop 100 measured With OSC1 =VSS.
6. Standard temperature range is 0° to 70°C.
7. Walt 100 is affected Irnearly by the OSC2 capacitance.
MOTOROLA MICROPROCESSOR DATA 3-1002
DC ELECTRICAL CHARACTERISTICS
(VOO = 33 Vdc::+:: 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Output Voltage, ILoad-s:10 0 J.lA VOL - - 01 V
VOH VOO-O 1 -
-Output High Voltage (see Figure 13) VOH V
(lLoad = 0.2 mAl PA7-PAO, PB7-PB5, PC7-PCO, P05, TCMP VOO-O 3 -
-Output Low Voltage (see Figure 14) VOL
- -
0.3 V(lLoad = 04 mAl PA7-PAD, PB7-PB5, PC7-PCO, P05, TCMP
Input High Voltage VIH 0.7 xVOO
-
VOO VPA7-PAD, PB7-PB5, PC7-PCO, P05, P07ITCAP, IRQ, RESET,OSCl
Input Low Voltage VIL VSS - O. 2xVOO V
PA7-PAD, PB7-PB5, PC7-PCO, P05, P07/TCAP, IRQ, RESET,OSCl
Data Retention Mode (0' to 70'C) VRM 2.0 - - V
Supply Current (see Notes) 100
Run (see Figures 15 and 17)
-
10 25 mAWalt (see Figures 15 and 17) - 0.5 1.4 mA
Stop (see Figure 17)
25°C
-
10 30 J.lA0° to 70cC (Standard) - - 80 J.lA
liO Ports HI-Z Leakage Current IlL - - ::,::10 J.lA
PA7-PAO, PB7-PB5, PC7-PCO, P05
Input Current lin - - ::+::1 J.lA
RESET, IRQ, OSC1, P05, P07/TCAP
CapaCItance pF
Ports (as Input or Output) Cout
- -
12RESET, IRQ, P05, P07/TCAP Cln - - 8
NOTES:
1 All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3 Run (Operating) 100. Walt 100 Measured uSing external square wave clock source (fosc = 4.2 MHz), all Inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
4 Walt, Stop 100 All ports configured as Inputs, VIL = 0.2 V, VIH = VOO - 02 V.
5. Stop 100 measured with OSC1 = VSS.
6 Standard temperature range IS 0° to 70°C.
7 Walt 100 IS affected linearly by the OSC2 capacitance.
MOTOROLA MICROPROCESSOR DATA 3-1003
I
I
MC68HC05P1
DC ELECTRICAL CHARACTERISTICS
(VOO = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted) Characteristic
Output Voltage, ILoad!S 100 f-LA
Output High Voltage (see Figure 13)
((Load = 0.8 rnA) PA7-PAD, PB7-PB5, PC7-PCO, P05, TCMP Output Low Voltage (see Figure 14)
((Load = 1.6 rnA) PA7-PAD, PB7-PB5, PC7-PCO, P05, TCMP Input High Voltage
PA7-PAD, PB7-PB5, PC7-PCO, P05, PD7ITCAP, IRQ, RESET,OSC1
Input Low Voltage
PA7-PAD, PB7-PB5, PC7-PCO, P05, P07/TCAP, IRQ, RESET,OSC1
Oata Retention Mode (00 to 70nC) Supply Current (see Notes)
Run (see Figures 15 and 16) Walt (see Figures 15 and 16) Stop (see Figure 16)
25°C
on
to 70"C (Standard) 10 Ports HI-Z Leakage CurrentPA7-PAO, PB7-PB5, PC7-PCO, P05 Input Current
RESET, IRQ, OSC1, P05, P07/TCAP Capacitance
Ports (a~ut or Output) RESET, IRQ, PD5, P07/TCAP NOTES:
All values shown reflect average measurements.
TYPical values at midpoint of voltage range, 25"C only
Symbol VOL VOH VOH
VOL
VIH
VIL
VRM 100
IlL
lin
Cout Cin
Min Typ Max Unit
-
- 0.1 VVOD-0.1
-
-V
VOD-0.8
-
--
-
04 V07xVOO
-
VOO VVSS
-
0.2x VOO V2.0
- -
V- 3.5 70 rnA
-
1.6 4.0 rnA-
20 50 f-LA- - 140 f-LA
- - ±10 f-LA
- -
±1 f-LApF
- - 12
- - 8
Run (Operating) 100, Walt 100. Measured uSing external square wave clock source (fosc = 4.2 MHz). all Inputs 02 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
Walt, Stop 100: All ports configured as Inputs, VIL=0.2 V, VIH=VOO-O 2 V.
Stop 100 measured with OSC1 = VSS.
Standard temperature range IS 0° to 70°C.
7. Walt 100 IS affected linearly by the OSC2 capacitance.
MOTOROLA MICROPROCESSOR DATA 3·1004
50,---,,---.---.---,
40;---~~----~---~--~~
30~----~~----~--20;---~~--~~---~----~
I 0 ~----_F'_#
02 04 06 08
VOO-VOH /VOLTS)
Figure 13. Typical VOH vs IOH for Ports A, B, C, and TCMP
35
30
25
20
~ ~
-S -S
D D
P p
I 5
10
05
05 10 15 20
INTERNAL FREQUENCY I/tcycle (MHz)
60~---,---.---,---,
50~----~---;---r-~~~
404---~~----~---~ -S 304---~~----~~~--~----~
20~----_4--_#~+---_+----__;
10;---~~----~---~----~
01 02 03 04
VOL (VOLTS)
Figure 14. Typical VOL vs IOL for All Ports
3 5 , - - - , - - - . - - - , - - - ,
30~----~---;---~~----~
254---4---4---~~----~
20
15
10
05
WAIT MODE
05 10
116 mAl
15 20
INTERNAL FREQUENCY I/tcycle (MHz) Figure 15. Typical Current vs Internal Frequency for Run and Wait Modes
MOTOROLA MICROPROCESSOR DATA 3-1005
II
<t E-o E
II
MC68HC05P1
70
VOO 5 V + 10%
60
50
40
30
20
10
STOP 100 1140 !lA, 0 - 70 C!
05 10 15
INTERNAL FREQUENCY lMHz!
Figure 16. Maximum 100 vs Frequency for VOO=5.0 Vdc
25
VOO = 3 3 V ~ 10%
20
15
«
E-o E 10
054---~~~~~---~----+---~
STOP 100 180 !lA, 00 - 700e!
02 04 06 08 10
INTERNAL FREQUENCY lMHz!
Figure 17. Maximum 100 vs Frequency for VOO=3.3 Vdc
MOTOROLA MICROPROCESSOR DATA 3-1006
20
CONTROL TIMING
(VOO=5.0 Vdc±10%, VSS=O Vdc, TA=lL to TH)
Characteristic Symbol Min Max Unit
Frequency of Operation fosc MHz
Crystal Option
-
4.2External Clock Option dc 4.2
Internal Operating Frequency fop MHz
Crystal (fosc -2)
-
2.1External Clock (fosc - 2) dc 2.1
Cycle Time (see Figure 20) tCYC 480 - ns
Crystal OSCillator Startup Time (see Figure 20) tOXOV
-
100 msStop Recovery Startup Time (Crystal OSCillator) (see Figure 18) tlLCH
-
100 msRESET Pulse Width (see Figure 20) tRL 1.5 - tcyc
Timer
Resolution** tRESL 4.0 - tcyc
Input Capture Pulse Width (see Figure 19) tTH, tTL 125
-
nsInput Capture Pulse Penod (see Figure 19) tTLTL *** - tCYC
Interrupt Pulse Width Low (Edge-Tnggered) (see Figure 8) tlLlH 125 - ns
Interrupt Pulse Period (see Figure 8) tlLlL *
-
tCYCOSC1 Pulse Width tOH, taL 90
-
ns*The minimum period tlLlL should not be less than the number of cycle times it takes to execute the Interrupt service routine plus 21 tcyc.
**Slnce a 2-blt prescaler In the timer must count four Internal cycles (tcyel, this IS the limiting minimum factor In determining the timer resolution.
***The minimum period tTL TL should not be less than the number of cycle times It takes to execute the capture Interrupt service routine plus 24 tcyc.
OSC1'
~IIIIIIIIIII ~ IIIIIIIIIZt.
tRL RESET
i-+----tILCH - - - + - 1 ... -4064 teye
INTERNAL
CLOCK - - - -...
INTERNAL
~
ADDRESS
)I.)('lYYYYXXX'f.:!.:!Y...
lFFE lFFE lFFE lFFE lFFF4BUS ~
NOTES:
1. Represents the Internal gating of the OSC1 pin 2 IRQ pin edge-sensitive mask option 3 IRQ pin level- and edge-sensitive mask option.
4 RESET vector address shown for timing example
Figure 18. Stop Recovery Timing Diagram