SYNERTEIt Range (-55°C 'to' + t 25° C)
PRELIMINARYA SUBSIDIARY OF HONEYWELL
I
.Cc
" 70 ns Maximum Access
" No Clocks or Strobes Required
" Automatic CS Power Down .. Identical Cycle and Access. Times
III Single +5V Supply (±10%)
The Synertek SYM2148 is a 4096-Bit Static Random Access Memory organized 1024 words by 4 bits and is fabricated using Synertek's new N-Channel Silicon-Gate HMOS ,technology, It is designed using fully stat-ic circuitry, therefore requiring no clock or refreshing to operate. Address set-up times are not required and the data is read out non-destructively with the sarne polarity as the input data. Common data input and output pins provide maximum design flexibility.The three-state output facilitates memory expansion by allowing the outputs to be OR-tied to other devices.
PIN CONFIGURATION
A6 Vee
A5 A7
A4 As
A3 A9
Ao I/OT
AT 1/02
A2 1/03
cs
1/04GND WE
ORDERING INFORMATION
Access Operating Standby
Order Time Cu'rrent Current Package Number (Max) (Max) (Max) Type SYMC2148 70n. 150mA 30mA Ceramic
• Industry Standard 2114 Pinout
• Totally TTL Compatible All Inputs and Outputs
• Common Data Input and Output
• High Density.18,Pin Package
• Three-State Output
The SYM2148 offers an automatic power'downfea-ture_ 'Power down is controlled by the Chip Select input. When Chip Select (CS) goes high, thus de.
selecting the SYM2148, the.device will automatically power down and remain, in a standby power mode as long as CS remains high. This unique feature provides system level power savings as much as 85%.
The SYM2148 is packaged in an l8-pin DIP for the highest possible density. The device is fully TTL com-patible and has a single +5V power supply. ,
ROW SELECT
BLOCK DIAGRAM
MEMORY ARRAY 64 ROWS 64 COLUMNS
_ V e e
SYMD2148 70n. 150mA 30m A Cerdip
SYMF2148 70n. 150mA 30mA ' Flatpak cs
--..--<1-'
SYMC2148-6 85n. 150mA 30mA Ceramic SYMD2148-6 85n. 150mA 30mA Cerdip
SYMF2148-6 85n. 150mA 30mA Flatpak WE -*---1_J
1-44
A SUBSIDIARY OF HONEYWELL
• 45 ns Maximum Address Access
• Fully Static Operation:
No Clocks or Strobes Required
• Fast Ch ip Select Access Time: 20ns Max.
• Identical Cycle and Access Times
• Single +5V Supply
The Synertek SY2149H is a 4096·Bit Static Random Access Memory organized 1 024words by 4 bits and is fabricated using Synertek's new N-Channel Silicon·
Gate HMOS technology. It is designed using fully stat-ic circuitry, therefore requiring no clock or refreshing to operate. Address set·up times are not required and the data is read out non·destructively with the same polarity as the input data. Common data input and output pins provide maximum design flexibility. The three·state output facilitates memory expansion by allowing the outputs to be OR-tied to other devices.
PIN CONFIGURATION
A6 Vee
As A7
A4 As
A3 A9
An I/O,
A, 1/02
• Industry Standard 2114 Pinout
• Totally TTL Compatible:
All I nputs and Outputs
• Common Data I nput and Outputs
• High Density 18-Pin Package
• Three·State Output
SY2149H MEMORY PRODUCTS
The SY2149H offers a chip select access that is faster than its address access. In a typical application, the address access begins as soon as the address is val id.
At this time,. the high order addresses are decoded and the desired memory is then selected. With the faster chip select access, this decode time wil) not add to the overall access time thus significantly im·
proving system performance.
The SY2149H is packaged in an 18-pin DIP for the highest possible density. The device is fully TTL com·
patible and has a single +5V power supply.
BLOCK DIAGRAM
MEMORY ARRAY
64 ROWS 64 COLUMNS
_ V e e _ G N D
A2 1/03 A8---'~
cs
1/04 A,---...-c.---,GND WE
ORDERING INFORMATION I/O, Access Supply
Order Time Current Package Number (Max) (Max) Type SYC2149H·2 45nsec 150mA Ceramic SYD2149H·2 45nsec 150mA Cerdip SYC2149H·3 55nsec 150mA Ceramic SYD2149H·3 55nsec 150mA Cerdip SYC21 49H L·3 55nsec 125mA Ceramic SYD2149HL·3 55nsec 125mA Cerdip
SYC2149H 70nsec 150mA Ceramic Cs
--..,....-<1-,
SYD2149H 70nsec 150mA Cerdip SYC2149HL 70nsec 125mA Ceramic SYD2149HL 70nsec 125mA Cerdip
WE --~-t_J
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias . . . • • . . . -10°C to 85°C Storage Temperature . . . -65°C to 150°C Voltage on Any Pin with
Respect to Ground . . . .. -3.5V to +7V Power Dissipation . . . • . . . • . • . . • 1.0W
SY2t49H
COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
D.C.
CHARACTERISTICS TA = O°C to +70°C, VCC = 5V ±10% (Unless otherwise specified) (Note 6) 2149H·2,2149H·3,2149HL·3,2149HL· 2149H
Symbol Parameter Min. Max. Min. Max. Unit Conditions
III Input Load Current 10 10 JlA VCC = Max, V,N = Gnd to VCC
(All input pins).
ILO Output Leakage Current 50 50 JlA CS = V'H, VCC = Max
VOUT = Gnd to 4.5V
ICC Power Supply Current 115 140 mA TA = 25°C
J
VCC = Max, CS = V,L125 150 mA T A = 0 C
1
Outputs OpenV,L I nput Low Voltage -3.0 0.8 -3.0 0.8 V
V,H Input High Voltage 2.0 6.0 2.0 6.0 V
VOL Output Low Voltage 0.4 0.4 V 'OL =8mA
VOH Output High Voltage 2.4 2.4 V 10H =-4.0 mA
lOS Output Short Circuit ·±200 ±200 mA VOUT = GND to VCC
Current
CAPACITANCE TA = 25°C, f= 1.0MHz
Symbol Test Typ. Max. Unit
COUT Output Capacitance 7 pF
CIN Input Capacitance 5 pF
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS TA = O°C to +70°C, VCC = 5V ±10% (Unless otherwise specified) (Note 6) READ CYCLE
2149HL·3 2149HL 2149H·2 2149H·3 2149H
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Conditions
tRC Read Cycle Ti me 45 55 70 ns
tAA Address Access Time 45 55 70 ns
tACS Chip Select Access Time 20 25 30 ns
tOH Output Hold from Address Change 5 5 5 ns
tLZ Chip Selection to Output in Low Z 5 5 5 ns Note 5
tHZ Chip Deselectio to Output in High Z 0 15 0 15 0 15 ns Note 5 WRITE CYCLE
twc Write Cycle Time 45 55 70 ns
tew Chip Selection to End of Write 40 50 65 ns
tAW Address Valid to End of Write 40 50 65 ns
tAS Address Setup Time 0 0 0 ns
twp Write Pulse Width 35 40 50 ns
twR Write Recovery Time 5 5 5 ns
tow Data Val id to End of Write 20 20 25 ns
tDH Data Hold Time 0 0 0 ns
twz Write Enabled to Output in High Z 0 15 0 20 0 25 ns Note 6
tow Output Active from End of Write 0 0 0 ns Note 5
-(See follOWIng page for notes)
SY2t49H
TIMING DIAGRAMS
READ CYCLE NO.1 (Notes 1 and 2)
'""~~ t
IOH IAAIXX
IRC~ *
DATA OUT PREVIOUS DATA VALID DATA VALID
READ CYCLE NO.2 (Notes 1 and 3)
IRC
CS~
lACS
i I H Z -ILZ
HIGH IMPEDANCE
XX
HIGHDATA OUT DATA VALID
IMPEDANCE
WRITE CYCLE NO.1 (WE controlled) (Note 4)
IWC
ADDRESS~
ICW
.
cs \ I I I I I I
lAW
I W R
-lAS
I
IWpWE
\ \
lOW
.
tOH --.DATA IN
-;
DATA VALID- I W Z - ' IOW
-HIGH IMPEDANCE
DATA OUT DATA UNDEFINED
NOTES:
1. WE is high for Read Cycles.
2. Device is continuously selected, CS = VIL.
3. Addresses valid.
4. If CS goes high simultaneously with WE high, the outputs remain in the high impedance state.
S. Transition is measured t500mV from low or high impedance voltage with load B. This perameter is sampled and not 100% tested.
6. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
SYZ149H
WRITE CYCLE NO.2 (CS controlled) (Note 4)
twe
,~ '-..J
ADDRESS
_ t A S tew
--- ' ~
tAW
I w R
-twp
\ \ \ \ \ \ \ \ \ \ \ .., / / / / / / / / ,
tow t
OH_
DATA IN -l DATA VALID
...--twz