SYNERTEK
A SUBSIDIARY OF HONEYWELL
200 ns Maximum Access
• •
Low Power: 0.1 mW/Bit Operating• •
•
.03 mW/Bit Standby No Clocks or Strobes Required Identical Cycle and Access Times Single Supply: +5VOperating
+2.5V Standby
The SY21l4LV is a 4096·Bit static Random Access Memory organized 1024 words by 4·bits and is fabri·
cated using Synertek's N·channel Silicon· Gate MOS technology. These advanced processing techniques allow the SY21l4LV to- maintain memory with VCC reduced to 2.5V. This reduces standby power by 60% and simplifies the design of battery back·up systems. It is designed using fully DC stable (static) circuitry in both the memory array and the decoding and therefore requires no clock or refreshing to operate. Address setup times are not required and the data is read out nondestructively with the same polarity as the input data. Common Input/Output pins are provided to simplify design of the bus oriented systems, and can drive 2 TTL loads.
PIN CONFIGURATION
A, Vee
AS A,
A, A8
AJ A.
AO liD,
A, 1'°2
A2 11°3
oS 1'°4
GND WE
ORDERING INFORMATION Supply
Order Package Access CUrrent Temperature Number Type Time IMax) Range SYD2114LV Cerdip 450nsec 70mA O°C to +70° C . SYP2114LV Molded 450nsec 70mA o"C to +70°C SYD2114LV-3 Cerdip 300nsec 70mA O°Cto +70°C SYP2114LV-3 Molded 300nsec 70mA O°C to +70°C SYD2114LV-2 Cerdip 200nsec 70mA O°C to +70°C SYP2114LV-2 Molded 200nsee 70mA O°C to +70°C
• Totally TTL Compatible:
All I nputs, Outputs, and Power Supply
• Common Data I/O o 400 mv Noise Immunity
• High Density 18 Pin Package
The SY2ll4LV is designed for memory applications where high performance, low power, large bit storage and simple interfacing are important design objectives.
.It is totally TTL compatible in all respects: inputs.
outputs, and the single +5V supply. A separate Chip Select (CS) input allows easy selection of an individ·
ual device when outputs are or·tied.
The SY2114LV is packaged in an l8·pin DIP for the highest possible density and is fabricated with N·
channel, Ion Implanted, Silicon·Gate technology - a technology providing excellent performance charac·
teristics as well as improved protection against con·
tamination.
A O - - - . , A, _ _ _ . ,
ID,---...., '0,
---ff-H 10J--ti+HWE
BLOCK DIAGRAM
MEMORY ARRAY 64 ROWS 64 COLUMNS
Vee
GND
ABSOLUTE MAXIMUM RATINGS Temperature Under Bias
Storage Temperature Voltage on Any Pin with
Respect to Ground Power Dissipation
-10°C to SO°C _65°C to 150°C -0.5V to +7 V 1.0W
Sf2t t4LV
COMMENT
Stresses above those listed under "Absolute Maximum Rat-ings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
D.C. CHARACTERISTICS TA ~ O°C to +70°C, Vee ~ 5V ± 5% (Unless otherwise specified) 2114LV-2,
2114LV-3,2114LV
Symbol Parameter Min Max Unit Conditions
III I nput Load Current 10 /lA VIN ~ 0 to 5.25V
(All input pins)
ILO I/O Leakage Current 10 /lA CS ~ 2.0V,
VI/O ~ O.4V to VCC
ICC1 Power Supply Current 65 mA Vce ~ 5.25V, 11/0 ~ 0 mA,
TA~25°C
ICC2 Power Supply Current 70 mA I Vce ~ 5.25V, 11/0 = 0 mA,
TA ~ O°C
VIL Input Low Voltage -0.5 O.S V
VIH Input High Voltage 2.0 Vee V
VOL Output Low Voltage 2.4 0.4 V 10L ~ 3.2 mA
VOH Output High Voltage Vee V 10H ~ -1.0 mA
CAPACITANCE TA ~ 25°C, f ~ 1.0 MHz
Symbol Test Typ Max Units
CliO Input/Output Capacitance 5 pF
CIN Input Capacitance 5 pF
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS T A ~ O°C to 70°C, VCC ~ 5V ±5% (Unless Otherwise Specified)
2114LV-2 2114LV-3 2114LV
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRe Read Cycle Time 200 300 450 nsec
tA Access Time 200 300 450 nsec
teo Chip Select to Output Valid 70 100 120 nsec
tex Chip Select to Output Enabled 20 20 20 nsec
tOTD Chip Deselect to Output Off 0 60 0 SO 0 100 nsec
tOHA Output Hold From Address Change 50 50 50 nsec
Write Cycle
twe Write Cycle Time 200 300 450 nsec
tAW Address to Write Setup Time 0 0 0 nsec
tw Write Pulse Width 120 150 200 nsec
tWR Write Release Time 0 0 0 nsec
tOTW Write to Output Off 0 60 0 SO 0 100 nsec
tDW Data to Write Overlap 120 150 200 nsec
tDH Data Hold 0 0 0 nsec
A.C. Test Conditions
Input Pulse Levels . . . O.SV to 2.0V Input Rise and Fall Time . . . 10 n sec Timing Measurement Levels: Input . . . 1.5V Output . . . .. O.S and 2.0V Output Load . . . HTL Gate and 100pF
1-22
STANDBY CHARACTERISTICS T A ~ O°C to 70°C
Symbol Parameter Min. Max. Unit Test Conditions
VPD VCC in Standby 2.5 V
Vcss(2) CS Bias in Standby 2.5 V 2.5V';; VPD';; VCC Max.
IpD Standby Current Drain 50 mA All Inputs ~ \lPD ~ 2.5V ,
tcp Chip Deselect to Standby
a
nsTime
tR Standby Recovery Time 500 ns
TIMING DIAGRAMS Write Cycle
Read Cycle (3)
i
twc IIRC I ADDRESS
===* *==
IA ,
~~-tw@-~
ADDRESS
==x
!c=
Ics~ teo
~
l - t O T D - !
DOUT
- ' - - t c X - . _ _ ~IOHAh ' ~ I DOUT~ WE
t~w
-IOTW--I
, I , tow rtOH
I
D,N
~ ~
Standby Operation'
NOTES
-4--STANDBY 1. Typical values are for T A = 25°C and nominal
tcp-I - MODE tR supply voltage.
2. Consider the test conditions as shown: If the
vcc standby voltage (VPD) is between 5.25V (Vee
~ h
Max.l and 2.5V, then Cs must be held at 2.5V Min.3. WE is high for a Read Cycle.
4. tw is measured from the latter of CS or WE going
cs ®j ® ®
~
low to the earlier of CS or WE going high.ov -
~
-5. 4.75 Volts 6. 2.5 Volts
DATA STORAGE
When WE is high, the data input buffers are inhibited - WE low. The addresses must be properly established to prevent erroneous data from being written into during the entire Write time plus tWR.
the array. As long as WE remains high, the data stored Internal delays are such that address decoding prop-cannot be affected by the Address, Chip Select, or agates ahead of data inputs and therefore no address Data I/O logic levels or timing transitions. setup time is required. If the Write time precedes the Data storage also cannot be affected by WE, Addresses, addresses, the data in previously addressed locations, or the 'I/O ports as long as CS is high. Either CS or or some other location, may be changed. Addresses WE or both can prevent extraneous: writing due to must remain stable for the entire Write cycle but the
signal transitions. Data I nputs may change. The data which is stable
Data within the array can only be changed during - for tDW at the end of the Write time will be written Write time - defined as the overlap of CS low and into the addressed location.
TYPICAL CHARACTERISTICS
INPUT VOLTAGE LIMITS VS TEMPERATURE
CERDIP PACKAGE MOLDED PACKAGE
~
0.900 (22.860) MAX---l0.060 I 1.5241.r:;::::::::::::::::=====:::::j ~o.;;iO(4.57:
0", r"¥WWWW,:;.;:::===
-! . ~ ~ ~
-I~"""'-'--0.11012.7941 0.07011.7781 0.02310.5841 0.090 (2.286) '0.030 (0,762) 0.015 {a.38ll